From a3c9680d1e2b84693759747a4779341ba80c4a50 Mon Sep 17 00:00:00 2001
From: Henry Cook
Date: Wed, 4 Nov 2015 09:21:07 -0800
Subject: Remove Parameters library and refactor Driver.

In addition to removing all the extraneous Driver invocations that created various top-level Parameters instances,
this commit also lays the groundwork for stanza-firrtl/verilator based testing of Modules that extend BasicTester.

The execution-based tests have been updated accordingly. They will only succeed if firrtl and verilator binaries have been installed.
Further work is needed on individual tests to use assertions instead of .io.error.
---
 src/main/resources/top.cpp | 91 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)
 create mode 100644 src/main/resources/top.cpp

(limited to 'src/main/resources/top.cpp')

diff --git a/src/main/resources/top.cpp b/src/main/resources/top.cpp
new file mode 100644
index 00000000..8951032e
--- /dev/null
+++ b/src/main/resources/top.cpp
@@ -0,0 +1,91 @@
+#include <verilated.h>
+#include <iostream>
+
+#if VM_TRACE
+# include <verilated_vcd_c.h>	// Trace file format header
+#endif
+
+using namespace std;
+
+//VGCDTester *top;
+TOP_TYPE *top;
+
+vluint64_t main_time = 0;       // Current simulation time
+        // This is a 64-bit integer to reduce wrap over issues and
+        // allow modulus.  You can also use a double, if you wish.
+
+double sc_time_stamp () { // Called by $time in Verilog
+  return main_time;       // converts to double, to match
+                          // what SystemC does
+}
+
+// TODO Provide command-line options like vcd filename, timeout count, etc.
+const long timeout = 100000000L;
+
+int main(int argc, char** argv) {
+  vluint32_t done = 0;
+  Verilated::commandArgs(argc, argv);   // Remember args
+  top = new TOP_TYPE;
+
+#if VM_TRACE			// If verilator was invoked with --trace
+    Verilated::traceEverOn(true);	// Verilator must compute traced signals
+    VL_PRINTF("Enabling waves...\n");
+    VerilatedVcdC* tfp = new VerilatedVcdC;
+    top->trace (tfp, 99);	// Trace 99 levels of hierarchy
+    tfp->open ("dump.vcd");	// Open the dump file
+#endif
+
+
+  top->reset = 1; 
+
+  cout << "Starting simulation!\n";
+
+  while (!Verilated::gotFinish() && !done && main_time < timeout) {
+    if (main_time > 10) {
+      top->reset = 0;   // Deassert reset
+    }
+    if ((main_time % 10) == 1) {
+      top->clock = 1;       // Toggle clock
+    }
+    if ((main_time % 10) == 6) {
+      top->clock = 0;
+    }
+    top->eval();               // Evaluate model
+#if VM_TRACE
+	if (tfp) tfp->dump (main_time);	// Create waveform trace for this timestamp
+#endif
+    done = top->io__024done;
+    main_time++;               // Time passes...
+  }
+
+  // Run for 10 more clocks
+  vluint64_t end_time = main_time + 100;
+  while (main_time < end_time) {
+    if ((main_time % 10) == 1) {
+      top->clock = 1;       // Toggle clock
+    }
+    if ((main_time % 10) == 6) {
+      top->clock = 0;
+    }
+    top->eval();               // Evaluate model
+#if VM_TRACE
+	if (tfp) tfp->dump (main_time);	// Create waveform trace for this timestamp
+#endif
+    main_time++;               // Time passes...
+  }
+
+#if VM_TRACE
+    if (tfp) tfp->close();
+#endif
+
+  if (main_time >= timeout)
+    cout << "Simulation terminated by timeout at cycle " << main_time << endl;
+  else 
+    cout << "Simulation completed at cycle " << main_time << endl;
+
+  int error = top->io__024error;
+  cout << "Simulation return value: " << error << endl;
+
+  return error;
+}
+
-- 
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