From 36506c527ff0f51636beee4160f0ce1f6ad2f90a Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Wed, 15 Dec 2021 15:53:52 +0800
Subject: Refactor TruthTable to use Seq (#2217)

This makes the resulting Verilog from decoding a TruthTable deterministic.---
 .../scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala   | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'integration-tests/src/test/scala/chiselTests/util/experimental/minimizer')

diff --git a/integration-tests/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala b/integration-tests/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
index a932eb77..07afd074 100644
--- a/integration-tests/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
+++ b/integration-tests/src/test/scala/chiselTests/util/experimental/minimizer/MinimizerSpec.scala
@@ -19,7 +19,7 @@ class DecodeTestModule(minimizer: Minimizer, table: TruthTable) extends Module {
   chisel3.experimental.verification.assert(
     // for each instruction, if input matches, output should match, not no matched, fallback to default
     (table.table.map { case (key, value) => (i === key) && (minimizedO === value) } ++
-      Seq(table.table.keys.map(i =/= _).reduce(_ && _) && minimizedO === table.default)).reduce(_ || _)
+      Seq(table.table.map(_._1).map(i =/= _).reduce(_ && _) && minimizedO === table.default)).reduce(_ || _)
   )
 }
 
-- 
cgit v1.2.3