From 2f890aabc1ecf04c6efcb84cee4f00da67be6a53 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 25 Oct 2022 01:58:03 +0000 Subject: Add Scalafmt for mill (backport #2805) (#2807) * Add Scalafmt for mill (#2805) * add scalafmt for test in mill build system. * reformat codes in integration-tests (cherry picked from commit d881fd29d7af91a7c514565b4b21797f1e44fbdb) # Conflicts: # build.sc # integration-tests/src/test/scala/chiselTests/util/experimental/BitPat.scala * Resolve backport conflicts Co-authored-by: Jiuyang Liu Co-authored-by: Jack Koenig --- .../scala/chiselTests/util/experimental/algorithm/Bitwise.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'integration-tests/src/test/scala/chiselTests/util/experimental/algorithm') diff --git a/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala b/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala index 6c8eb4b4..d0f16701 100644 --- a/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala +++ b/integration-tests/src/test/scala/chiselTests/util/experimental/algorithm/Bitwise.scala @@ -11,7 +11,7 @@ class ScanLeftOrTestModule(width: Int) extends Module { val input = IO(Input(UInt(width.W))) var lsb = false.B - val vec = for(b <- input.asBools) yield { + val vec = for (b <- input.asBools) yield { val cur = b || lsb lsb = cur cur @@ -34,13 +34,13 @@ class ScanRightOrTestModule(width: Int) extends Module { class scanOrTest extends AnyFlatSpec with ChiselScalatestTester with Formal { "scanLeftOr" should "compute correctly" in { - for(i <- 1 to 16) { + for (i <- 1 to 16) { verify(new ScanLeftOrTestModule(i), Seq(BoundedCheck(1))) } } "scanRightOr" should "compute correctly" in { - for(i <- 1 to 16) { + for (i <- 1 to 16) { verify(new ScanRightOrTestModule(i), Seq(BoundedCheck(1))) } } -- cgit v1.2.3