From 2f890aabc1ecf04c6efcb84cee4f00da67be6a53 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 25 Oct 2022 01:58:03 +0000 Subject: Add Scalafmt for mill (backport #2805) (#2807) * Add Scalafmt for mill (#2805) * add scalafmt for test in mill build system. * reformat codes in integration-tests (cherry picked from commit d881fd29d7af91a7c514565b4b21797f1e44fbdb) # Conflicts: # build.sc # integration-tests/src/test/scala/chiselTests/util/experimental/BitPat.scala * Resolve backport conflicts Co-authored-by: Jiuyang Liu Co-authored-by: Jack Koenig --- integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'integration-tests/src/test/scala/chiselTest') diff --git a/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala b/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala index 35d1a299..20f3443a 100644 --- a/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala +++ b/integration-tests/src/test/scala/chiselTest/MemFormalSpec.scala @@ -10,12 +10,12 @@ import firrtl.annotations.MemoryArrayInitAnnotation import org.scalatest.flatspec.AnyFlatSpec class MemFormalSpec extends AnyFlatSpec with ChiselScalatestTester with Formal { - behavior of "SyncReadMem read enable" + behavior.of("SyncReadMem read enable") private def check(mod: Boolean => ReadEnTestModule, alwaysEnabeld: Boolean = false): Unit = { // we first check that the read is enabled when it should be verify(mod(true), Seq(BoundedCheck(4))) - if(!alwaysEnabeld) { + if (!alwaysEnabeld) { // now we check that it is disabled, when it should be // however, note that this check is not exhaustive/complete! assertThrows[FailedBoundedCheckException] { @@ -65,9 +65,9 @@ abstract class ReadEnTestModule(testShouldRead: Boolean) extends Module { }) // the first cycle after reset, the data will be arbitrary - val firstCycle = RegNext(false.B, init=true.B) + val firstCycle = RegNext(false.B, init = true.B) - if(testShouldRead) { + if (testShouldRead) { when(!firstCycle && RegNext(shouldRead)) { verification.assert(out === RegNext(addr)) } -- cgit v1.2.3