From d997acb05e5a307afb7c9ad4c136b9b4e1506efc Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Sun, 23 Oct 2022 19:01:43 +0000 Subject: Don't invalidate ExtModule ports in an explicitInvalidate = true context (backport #2795) (#2799) * Don't invalidate ExtModule ports in an explicitInvalidate = true context (#2795) * Don't invalidate ExtModule ports in an explicitInvalidate = true context ExtModule ports were previously invalidated in the emitted FIRRTL, which is correct in a NonStrict / `Chisel._` compatibility context but not in newer chisel3 code where `explicitInvalidate = true`. (cherry picked from commit 8e24a281545d25f6501dcc872eabdfb30bacd69d) # Conflicts: # core/src/main/scala/chisel3/BlackBox.scala * Resolve backport conflicts Co-authored-by: Jared Barocsi <82000041+jared-barocsi@users.noreply.github.com> Co-authored-by: Jack Koenig --- docs/src/cookbooks/cookbook.md | 2 ++ 1 file changed, 2 insertions(+) (limited to 'docs') diff --git a/docs/src/cookbooks/cookbook.md b/docs/src/cookbooks/cookbook.md index ac3a0c5d..e7485e66 100644 --- a/docs/src/cookbooks/cookbook.md +++ b/docs/src/cookbooks/cookbook.md @@ -791,6 +791,8 @@ class Salt extends Module { val io = IO(new Bundle {}) val drink = Module(new Coffee) override def desiredName = "SodiumMonochloride" + + drink.io.I := 42.U } ``` -- cgit v1.2.3