From 6c6409328034e06c4b722e87022029b287e9c90c Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Mon, 7 Mar 2022 08:00:47 +0000 Subject: Tweaks to the Verilog-vs-Chisel Page (#2432) (#2433) * Tweaks to the Verilog-vs-Chisel Page * Update cookbook.md * Update verilog-vs-chisel.md * Update verilog-vs-chisel.md (cherry picked from commit 7432bdff8369ba55db73c7934e41bb6f4060bb6d) Co-authored-by: Megan Wachs --- docs/src/cookbooks/cookbook.md | 1 - docs/src/cookbooks/verilog-vs-chisel.md | 15 ++++++++------- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'docs') diff --git a/docs/src/cookbooks/cookbook.md b/docs/src/cookbooks/cookbook.md index ea5892c3..118db228 100644 --- a/docs/src/cookbooks/cookbook.md +++ b/docs/src/cookbooks/cookbook.md @@ -31,7 +31,6 @@ Please note that these examples make use of [Chisel's scala-style printing](../e * [How can I dynamically set/parametrize the name of a module?](#how-can-i-dynamically-setparametrize-the-name-of-a-module) * Directionality * [How do I strip directions from a bidirectional Bundle (or other Data)?](#how-do-i-strip-directions-from-a-bidirectional-bundle-or-other-data) - * [Side-by-Side Comparison of Verilog to Chisel](verilog-vs-chisel.md) ## Type Conversions diff --git a/docs/src/cookbooks/verilog-vs-chisel.md b/docs/src/cookbooks/verilog-vs-chisel.md index 93fd5316..1adf609e 100644 --- a/docs/src/cookbooks/verilog-vs-chisel.md +++ b/docs/src/cookbooks/verilog-vs-chisel.md @@ -1,7 +1,14 @@ +--- +layout: docs +title: "Verilog-vs-Chisel" +section: "chisel3" +--- + # Verilog vs Chisel Side-By-Side + This page serves as a quick introduction to Chisel for those familiar with Verilog. It is by no means a comprehensive guide of everything Chisel can do. Feel free to file an issue with suggestions of things you'd like to see added to this page. ```scala mdoc:invisible @@ -126,11 +133,6 @@ class ParameterizedWidthAdder( ``` - - - - - @@ -688,8 +690,7 @@ ChiselStage.emitVerilog(new ReadWriteMem) Verilog Chisel - Generated Verilog - + -- cgit v1.2.3