From 7e4d1eeb03fddff735e67e3fe36b6efbfac39711 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Thu, 21 Jan 2021 17:07:45 -0800
Subject: Update docs for the removal of val io and MultiIOModule

---
 docs/src/wiki-deprecated/ports.md | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'docs/src/wiki-deprecated/ports.md')

diff --git a/docs/src/wiki-deprecated/ports.md b/docs/src/wiki-deprecated/ports.md
index f8c30b7a..e2b70050 100644
--- a/docs/src/wiki-deprecated/ports.md
+++ b/docs/src/wiki-deprecated/ports.md
@@ -30,21 +30,21 @@ provide powerful wiring constructs described later.
 
 (Chisel 3.2+)
 
-Chisel 3.2+ introduces an API `DataMirror.modulePorts` which can be used to inspect the IOs of any Chisel module, including MultiIOModules, RawModules, and BlackBoxes.
+Chisel 3.2+ introduces an API `DataMirror.modulePorts` which can be used to inspect the IOs of any Chisel module, including Modules, RawModules, and BlackBoxes.
 
 Here is an example of how to use this API:
 
 ```scala
 import chisel3.experimental.DataMirror
 
-class Adder extends MultiIOModule {
+class Adder extends Module {
   val a = IO(Input(UInt(8.W)))
   val b = IO(Input(UInt(8.W)))
   val c = IO(Output(UInt(8.W)))
   c := a +& b
 }
 
-class Test extends MultiIOModule {
+class Test extends Module {
   val adder = Module(new Adder)
   // for debug only
   adder.a := DontCare
-- 
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