From 58fa3c1118d9e892895970d48e2ba8a3c182bb81 Mon Sep 17 00:00:00 2001 From: Adam Izraelevitz Date: Mon, 26 Oct 2020 16:48:44 -0700 Subject: Fix crosslinks in mdoc. Can't use md suffix (#1640) * Fix crosslinks in mdoc. Can't use md suffix * Removed all .md crossrefs Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>--- docs/src/wiki-deprecated/faqs.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'docs/src/wiki-deprecated/faqs.md') diff --git a/docs/src/wiki-deprecated/faqs.md b/docs/src/wiki-deprecated/faqs.md index dfb01afe..45694cdc 100644 --- a/docs/src/wiki-deprecated/faqs.md +++ b/docs/src/wiki-deprecated/faqs.md @@ -24,7 +24,7 @@ We recommend the [Chisel Bootcamp](https://github.com/freechipsproject/chisel-bo ### How do I do ... (e.g. like that in Verilog) in Chisel? -See the [cookbook](cookbook.md). +See the [cookbook](cookbook). ### How can I contribute to Chisel? @@ -78,7 +78,7 @@ Chisel Modules are written by defining a [Scala class](http://docs.scala-lang.or ### Why Chisel? -Borrowed from [Chisel Introduction](introduction.md) +Borrowed from [Chisel Introduction](introduction) >We were motivated to develop a new hardware language by years of struggle with existing hardware description languages in our research @@ -226,7 +226,7 @@ res3: java.io.File = output.fir ### Why doesn't Chisel tell me which wires aren't connected? As of commit [c313e13](https://github.com/freechipsproject/chisel3/commit/c313e137d4e562ef20195312501840ceab8cbc6a) it can! -Please visit the wiki page [Unconnected Wires](unconnected-wires.md) for details. +Please visit the wiki page [Unconnected Wires](unconnected-wires) for details. ### What does `Reference ... is not fully initialized.` mean? @@ -235,7 +235,7 @@ It means that you have unconnected wires in your design which could be an indica In Chisel2 compatibility mode (`NotStrict` compile options), chisel generates firrtl code that disables firrtl's initialized wire checks. In pure chisel3 (`Strict` compile options), the generated firrtl code does not contain these disablers (`is invalid`). Output wires that are not driven (not connected) are reported by firrtl as `not fully initialized`. -Please visit the wiki page [Unconnected Wires](unconnected-wires.md) for details on solving the problem. +Please visit the wiki page [Unconnected Wires](unconnected-wires) for details on solving the problem. ### Can I specify behavior before and after generated initial blocks? Users may define the following macros if they wish to specify behavior before or after emitted initial blocks. -- cgit v1.2.3