From f39ec2ef5a3b2140b43d631056c2f974ca1895d5 Mon Sep 17 00:00:00 2001
From: Carlos Eduardo
Date: Wed, 14 Apr 2021 22:38:41 -0300
Subject: Fix doc formatting and generation (#1863)

* Remove space between backticks and language
* Make code examples in memories explanation work

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 docs/src/explanations/memories.md                  | 40 +++++++++++-----------
 .../polymorphism-and-parameterization.md           |  9 +++--
 docs/src/explanations/sequential-circuits.md       |  2 +-
 3 files changed, 27 insertions(+), 24 deletions(-)

(limited to 'docs/src/explanations')

diff --git a/docs/src/explanations/memories.md b/docs/src/explanations/memories.md
index 09ac4c8d..1f2f83be 100644
--- a/docs/src/explanations/memories.md
+++ b/docs/src/explanations/memories.md
@@ -10,36 +10,36 @@ Chisel provides facilities for creating both read only and read/write memories.
 
 ## ROM
 
-Users can define read only memories with a `Vec`:
+Users can define read-only memories by constructing a `Vec` with `VecInit`.
+`VecInit` can except either a variable-argument number of `Data` literals or a `Seq[Data]` literals that initialize the ROM.
 
 ```scala mdoc:invisible
 import chisel3._
+// This is bad, don't do this, use a val
+def counter = util.Counter(true.B, 4)._1
+val Pi = 3.14
+def sin(t: Double): Double = t // What should this be?
 ```
 
-``` scala mdoc:compile-only
-    VecInit(inits: Seq[T])
-    VecInit(elt0: T, elts: T*)
-```
-
-where `inits` is a sequence of initial `Data` literals that initialize the ROM. For example,  users cancreate a small ROM initialized to 1, 2, 4, 8 and loop through all values using a counter as an address generator as follows:
+For example, users can create a small ROM initialized to 1, 2, 4, 8 and loop through all values using a counter as an address generator as follows:
 
-``` scala mdoc:compile-only
-    val m = VecInit(Array(1.U, 2.U, 4.U, 8.U))
-    val r = m(counter(m.length.U))
+```scala mdoc:compile-only
+val m = VecInit(1.U, 2.U, 4.U, 8.U)
+val r = m(counter(m.length.U))
 ```
 
 We can create an *n* value sine lookup table using a ROM initialized as follows:
 
-``` scala mdoc:silent
-    def sinTable(amp: Double, n: Int) = {
-      val times =
-        (0 until n).map(i => (i*2*Pi)/(n.toDouble-1) - Pi)
-      val inits =
-        times.map(t => round(amp * sin(t)).asSInt(32.W))
-      VecInit(inits)
-    }
-    def sinWave(amp: Double, n: Int) =
-      sinTable(amp, n)(counter(n.U))
+```scala mdoc:compile-only
+def sinTable(amp: Double, n: Int) = {
+  val times =
+    (0 until n).map(i => (i*2*Pi)/(n.toDouble-1) - Pi)
+  val inits =
+    times.map(t => Math.round(amp * sin(t)).asSInt(32.W))
+  VecInit(inits)
+}
+def sinWave(amp: Double, n: Int) =
+  sinTable(amp, n)(counter(n.U))
 ```
 
 where `amp` is used to scale the fixpoint values stored in the ROM.
diff --git a/docs/src/explanations/polymorphism-and-parameterization.md b/docs/src/explanations/polymorphism-and-parameterization.md
index 94b896b1..9b69ed05 100644
--- a/docs/src/explanations/polymorphism-and-parameterization.md
+++ b/docs/src/explanations/polymorphism-and-parameterization.md
@@ -231,7 +231,10 @@ class X[T <: BaseModule with MyAdder](genT: => T) extends Module {
 println(ChiselStage.emitVerilog(new X(new Mod1)))
 println(ChiselStage.emitVerilog(new X(new Mod2)))
 ```
-```scala mdoc:passthrough
-println(ChiselStage.emitVerilog(new X(new Mod1)))
-println(ChiselStage.emitVerilog(new X(new Mod2)))
+
+Output:
+
+```scala mdoc:verilog
+ChiselStage.emitVerilog(new X(new Mod1))
+ChiselStage.emitVerilog(new X(new Mod2))
 ```
diff --git a/docs/src/explanations/sequential-circuits.md b/docs/src/explanations/sequential-circuits.md
index 938416ac..36bbb1aa 100644
--- a/docs/src/explanations/sequential-circuits.md
+++ b/docs/src/explanations/sequential-circuits.md
@@ -11,7 +11,7 @@ import chisel3._
 val in = Bool()
 ```
 The simplest form of state element supported by Chisel is a positive edge-triggered register, which can be instantiated as:
-``` scala mdoc:compile-only
+```scala mdoc:compile-only
 val reg = RegNext(in)
 ```
 This circuit has an output that is a copy of the input signal `in` delayed by one clock cycle. Note that we do not have to specify the type of Reg as it will be automatically inferred from its input when instantiated in this way. In the current version of Chisel, clock and reset are global signals that are implicitly included where needed.
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