From 9c026fd3a9beb2b39ad0d675afdcc31dbcc6819d Mon Sep 17 00:00:00 2001 From: Shorla Date: Fri, 22 Oct 2021 16:33:47 +0100 Subject: Add name to Naming Explanation page (#2199) * Update bundles-and-vecs.md * Update docs/src/explanations/bundles-and-vecs.md Co-authored-by: Megan Wachs * Update naming.md Added a title to the cookbook * Add name to Multiple Clock Domain page * Update multi-clock.md Co-authored-by: Megan Wachs --- docs/src/explanations/multi-clock.md | 2 ++ docs/src/explanations/naming.md | 1 + 2 files changed, 3 insertions(+) (limited to 'docs/src/explanations') diff --git a/docs/src/explanations/multi-clock.md b/docs/src/explanations/multi-clock.md index 6e9afd5a..eafb5372 100644 --- a/docs/src/explanations/multi-clock.md +++ b/docs/src/explanations/multi-clock.md @@ -3,6 +3,8 @@ layout: docs title: "Multiple Clock Domains" section: "chisel3" --- +# Multiple Clock Domains + Chisel 3 supports multiple clock domains as follows. Note that in order to cross clock domains safely, you will need appropriate synchronization logic (such as an asynchronous FIFO). You can use the [AsyncQueue library](https://github.com/ucb-bar/asyncqueue) to do this easily. diff --git a/docs/src/explanations/naming.md b/docs/src/explanations/naming.md index 60c653aa..a9f21936 100644 --- a/docs/src/explanations/naming.md +++ b/docs/src/explanations/naming.md @@ -3,6 +3,7 @@ layout: docs title: "Naming" section: "chisel3" --- +# Naming Historically, Chisel has had trouble reliably capturing the names of signals. The reasons for this are due to (1) primarily relying on reflection to find names, (2) using `@chiselName` macro which had unreliable behavior. -- cgit v1.2.3