From f1ad5b58e8a749d558758288d03ce75bf6b8ff9c Mon Sep 17 00:00:00 2001
From: Megan Wachs
Date: Thu, 18 Mar 2021 16:47:58 -0700
Subject: Reorganize website docs (#1806)

Updates to chisel3 documentation for website:
* guard code examples with mdoc and fix errors encountered along the way
* move some website content here vs splitting the content across two repos
* Bring in the interval-types and loading memories content so that it will be visible from the website
* remove all references to the wiki (deprecated)
* Remove reference to Wiki from the README
* fix tabbing and compile of chisel3-vs-chisel2 section
* Appendix: faqs now guarded and compile
* FAQs: move to resources section---
 docs/src/explanations/explanations.md | 39 +++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 docs/src/explanations/explanations.md

(limited to 'docs/src/explanations/explanations.md')

diff --git a/docs/src/explanations/explanations.md b/docs/src/explanations/explanations.md
new file mode 100644
index 00000000..01894ad7
--- /dev/null
+++ b/docs/src/explanations/explanations.md
@@ -0,0 +1,39 @@
+---
+layout: docs
+title:  "Explanations"
+section: "chisel3"
+---
+
+# Explanations
+
+Explanation documentation gives background and context.
+They can also explain why things are so - design decisions,
+historical reasons, technical constraints.
+
+If you are just getting started with Chisel, we suggest you
+read these documents in the following order:
+
+* [Motivation](motivation)
+* [Supported Hardware](supported-hardware)
+* [Data Types](data-types)
+* [Bundles and Vecs](bundles-and-vecs)
+* [Combinational Circuits](combinational-circuits)
+* [Operators](operators)
+* [Width Inference](width-inference)
+* [Functional Abstraction](functional-abstraction)
+* [Ports](ports)
+* [Modules](modules)
+* [Sequential Circuits](sequential-circuits)
+* [Memories](memories)
+* [Interfaces and Connections](interfaces-and-connections)
+* [Black Boxes](blackboxes)
+* [Enumerations](enumerations)
+* [Functional Module Creation](functional-module-creation)
+* [Muxes and Input Selection](muxes-and-input-selection)
+* [Multiple Clock Domains](multi-clock)
+* [Reset](reset)
+* [Polymorphism and Paramterization](polymorphism-and-parameterization)
+* [Printing in Chisel](printing)
+* [Naming](naming)
+* [Unconnected Wires](unconnected-wires)
+* [Annotations](annotations)
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