From e6192ea75ce0d840b4b51a376921c2feecaa3b46 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 11 Nov 2020 13:13:54 -0800
Subject: Add custom mdoc modifier for emitted Verilog (#1666)

---
 docs/src/cookbooks/naming.md | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

(limited to 'docs/src/cookbooks')

diff --git a/docs/src/cookbooks/naming.md b/docs/src/cookbooks/naming.md
index 4caabaff..098ea898 100644
--- a/docs/src/cookbooks/naming.md
+++ b/docs/src/cookbooks/naming.md
@@ -5,7 +5,6 @@ section: "chisel3"
 ---
 
 ```scala mdoc:invisible
-import chisel3.internal.plugin._
 import chisel3._
 import chisel3.experimental.prefix
 import chisel3.experimental.noPrefix
@@ -57,8 +56,9 @@ class ExampleNoPrefix extends MultiIOModule {
 
   out := add
 }
-
-println(ChiselStage.emitVerilog(new ExampleNoPrefix))
+```
+```scala mdoc:verilog
+ChiselStage.emitVerilog(new ExampleNoPrefix)
 ```
 
 ### I am still not getting the name I want. For example, inlining an instance changes my name!
@@ -88,8 +88,9 @@ class MyLeaf extends MultiIOModule {
   val out = IO(Output(UInt(3.W)))
   out := in
 }
-
-println(ChiselStage.emitVerilog(new WrapperExample))
+```
+```scala mdoc:verilog
+ChiselStage.emitVerilog(new WrapperExample)
 ```
 
 This can be used to rename instances and non-aggregate typed signals.
-- 
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