From 01100fa9af0e34b9a4ddb87b8060e6e3178d4272 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Fri, 17 Jun 2022 04:34:16 +0000 Subject: [docs] Document partial register reset (#2582) (#2583) (cherry picked from commit d54a37a51b16fb6e46093265d65fd47d5318f67f) Co-authored-by: Jack Koenig --- docs/src/appendix/experimental-features.md | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'docs/src/appendix/experimental-features.md') diff --git a/docs/src/appendix/experimental-features.md b/docs/src/appendix/experimental-features.md index eb91c190..a85704c2 100644 --- a/docs/src/appendix/experimental-features.md +++ b/docs/src/appendix/experimental-features.md @@ -10,6 +10,7 @@ Chisel has a number of new features that are worth checking out. This page is a - [FixedPoint](#fixed-point) - [Module Variants](#module-variants) - [Bundle Literals](#bundle-literals) +- [Vec Literals](#vec-literals) - [Interval Type](#interval-type) - [Loading Memories for simulation or FPGA initialization](#loading-memories) @@ -52,7 +53,10 @@ class Example extends RawModule { chisel3.stage.ChiselStage.emitVerilog(new Example) ``` -Partial specification is allowed, defaulting any unconnected fields to 0 (regardless of type). +Partial specification is allowed, which results in "invalidated fields" as +described in [Unconnected Wires](../explanations/unconnected-wires). +Note that this can be used with `RegInit` to construct partially reset registers as +described in the [Cookbook](../cookbooks/cookbook#how-do-i-partially-reset-an-aggregate-reg). ```scala mdoc class Example2 extends RawModule { @@ -122,9 +126,10 @@ chisel3.stage.ChiselStage.emitVerilog(new VecExample1a) ``` The following examples all use the explicit form. -With the explicit form partial specification is allowed. -When used with as a `Reg` `reset` value, only specified indices of the `Reg`'s `Vec` -will be reset +With the explicit form partial specification is allowed, which results in +"invalidated fields" as described in [Unconnected Wires](../explanations/unconnected-wires). +Note that this can be used with `RegInit` to construct partially reset registers as +described in the [Cookbook](../cookbooks/cookbook#how-do-i-partially-reset-an-aggregate-reg). ```scala mdoc class VecExample2 extends RawModule { -- cgit v1.2.3