From 558df41db062a14f52617fc44edd0aff569afa67 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 7 Jul 2021 16:56:35 -0700
Subject: Fix ChiselEnum docs (#2016)

Also add newline to end of `verilog` modifier code blocks so that there
is always a newline between code blocks and following material.---
 docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'docs-target')

diff --git a/docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala b/docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala
index a76e412a..f41fff73 100644
--- a/docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala
+++ b/docs-target/src/main/scala/chisel3/docs/VerilogMdocModifier.scala
@@ -27,7 +27,7 @@ class VerilogMdocModifier extends PostModifier {
         case (None, _) => None
       }
     result match {
-      case Some(content) => s"```verilog\n$content```"
+      case Some(content) => s"```verilog\n$content```\n"
       case None          => ""
     }
   }
-- 
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