From 70da39e140e96a9302a94864f077529e02596ef5 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 19 Apr 2022 02:29:00 +0000 Subject: Allow creating memories without an implicit clock (#2494) (#2495) Fixes #2470 (cherry picked from commit 44165a259bb16733a41798edca6b554b13f1d54a) Co-authored-by: Kevin Laeufer --- core/src/main/scala/chisel3/Mem.scala | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'core') diff --git a/core/src/main/scala/chisel3/Mem.scala b/core/src/main/scala/chisel3/Mem.scala index 36984a3a..d6ab9c4b 100644 --- a/core/src/main/scala/chisel3/Mem.scala +++ b/core/src/main/scala/chisel3/Mem.scala @@ -56,7 +56,9 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) with SourceInfoDoc { _parent.foreach(_.addId(this)) - private val clockInst: Clock = Builder.forcedClock + // if the memory is created in a scope with an implicit clock (-> clockInst is defined), we will perform checks that + // ensure memory ports are created with the same clock unless explicitly specified to use a different clock + private val clockInst: Option[Clock] = Builder.currentClock protected def clockWarning(sourceInfo: Option[SourceInfo]): Unit = { // Turn into pretty String if possible, if not, Builder.deprecated will find one via stack trace @@ -132,7 +134,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) implicit sourceInfo: SourceInfo, compileOptions: CompileOptions ): T = { - if (warn && clock != clockInst) { + if (warn && clockInst.isDefined && clock != clockInst.get) { clockWarning(Some(sourceInfo)) } makePort(sourceInfo, idx, dir, clock) @@ -164,7 +166,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) )( implicit compileOptions: CompileOptions ): Unit = { - if (warn && clock != clockInst) { + if (warn && clockInst.isDefined && clock != clockInst.get) { clockWarning(None) } implicit val sourceInfo = UnlocatableSourceInfo @@ -223,7 +225,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt) compileOptions: CompileOptions ): Unit = { implicit val sourceInfo = UnlocatableSourceInfo - if (warn && clock != clockInst) { + if (warn && clockInst.isDefined && clock != clockInst.get) { clockWarning(None) } val accessor = makePort(sourceInfo, idx, MemPortDirection.WRITE, clock).asInstanceOf[Vec[Data]] -- cgit v1.2.3