From d0db0b8b4661e64a79e8b14a24a4fa1baace1c3d Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 26 Jan 2021 17:15:57 -0800
Subject: Fix incorrect comment in ScalaDoc (#1756)

---
 core/src/main/scala/chisel3/Reg.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'core/src')

diff --git a/core/src/main/scala/chisel3/Reg.scala b/core/src/main/scala/chisel3/Reg.scala
index b2b99cc1..bd9e5311 100644
--- a/core/src/main/scala/chisel3/Reg.scala
+++ b/core/src/main/scala/chisel3/Reg.scala
@@ -127,7 +127,7 @@ object RegNext {
   * val x = Wire(UInt())
   * val y = Wire(UInt(8.W))
   * val r1 = RegInit(x) // width will be inferred
-  * val r2 = RegInit(y) // width is set to 8
+  * val r2 = RegInit(y) // width will be inferred
   * }}}
   *
   * 3. [[Aggregate]] initializer - width will be set to match the aggregate
-- 
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