From b169f6db95f9778cf8968cc1042b7f810f9d8123 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Tue, 15 Nov 2022 05:28:10 +0000
Subject: fullModulePorts + Opaque Types Fix and Test (#2845) (#2846)

(cherry picked from commit 49feb083c69066988ca0666ea4249a86570e2589)

Co-authored-by: Megan Wachs <megan@sifive.com>---
 core/src/main/scala/chisel3/Data.scala | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

(limited to 'core/src')

diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala
index 50093333..dddc0d5d 100644
--- a/core/src/main/scala/chisel3/Data.scala
+++ b/core/src/main/scala/chisel3/Data.scala
@@ -256,8 +256,13 @@ package experimental {
     def fullModulePorts(target: BaseModule): Seq[(String, Data)] = {
       def getPortNames(name: String, data: Data): Seq[(String, Data)] = Seq(name -> data) ++ (data match {
         case _: Element => Seq()
-        case r: Record  => r.elements.toSeq.flatMap { case (eltName, elt) => getPortNames(s"${name}_${eltName}", elt) }
-        case v: Vec[_]  => v.zipWithIndex.flatMap { case (elt, index) => getPortNames(s"${name}_${index}", elt) }
+        case r: Record =>
+          r.elements.toSeq.flatMap {
+            case (eltName, elt) =>
+              if (r._isOpaqueType) { getPortNames(s"${name}", elt) }
+              else { getPortNames(s"${name}_${eltName}", elt) }
+          }
+        case v: Vec[_] => v.zipWithIndex.flatMap { case (elt, index) => getPortNames(s"${name}_${index}", elt) }
       })
       modulePorts(target).flatMap {
         case (name, data) =>
-- 
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