From 6048c973f0c1c6e80a7a9e8ef6cec71ef0695e68 Mon Sep 17 00:00:00 2001
From: mergify[bot]
Date: Thu, 3 Feb 2022 02:42:14 +0000
Subject: Tweak new mem port clock warnings (#2389) (#2391)

Use Builder.deprecated instead of Builder.warning so that the warnings
are aggregated by source locator to prevent spamming the screen with
duplicated warnings.

(cherry picked from commit 538e223ae81c8b66a4123303f6dab61c874aaa1e)

Co-authored-by: Jack Koenig <koenig@sifive.com>---
 core/src/main/scala/chisel3/Mem.scala | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

(limited to 'core/src')

diff --git a/core/src/main/scala/chisel3/Mem.scala b/core/src/main/scala/chisel3/Mem.scala
index 4b7c0815..3f37308c 100644
--- a/core/src/main/scala/chisel3/Mem.scala
+++ b/core/src/main/scala/chisel3/Mem.scala
@@ -9,7 +9,7 @@ import firrtl.{ir => fir}
 import chisel3.internal._
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl._
-import chisel3.internal.sourceinfo.{MemTransform, SourceInfo, SourceInfoTransform, UnlocatableSourceInfo}
+import chisel3.internal.sourceinfo.{MemTransform, SourceInfo, SourceInfoTransform, SourceLine, UnlocatableSourceInfo}
 
 object Mem {
 
@@ -57,6 +57,16 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
   _parent.foreach(_.addId(this))
 
   private val clockInst: Clock = Builder.forcedClock
+
+  protected def clockWarning(sourceInfo: Option[SourceInfo]): Unit = {
+    // Turn into pretty String if possible, if not, Builder.deprecated will find one via stack trace
+    val infoStr = sourceInfo.collect { case SourceLine(file, line, col) => s"$file:$line:$col" }
+    Builder.deprecated(
+      "The clock used to initialize the memory is different than the one used to initialize the port. " +
+        "If this is intentional, please pass the clock explicitly when creating the port. This behavior will be an error in 3.6.0",
+      infoStr
+    )
+  }
   // REVIEW TODO: make accessors (static/dynamic, read/write) combinations consistent.
 
   /** Creates a read accessor into the memory with static addressing. See the
@@ -123,10 +133,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
     compileOptions:      CompileOptions
   ): T = {
     if (warn && clock != clockInst) {
-      Builder.warning(
-        "The clock used to initialize the memory is different than the one used to initialize the port. " +
-          "If this is intentional, please pass the clock explicitly when creating the port. This behavior will be an error in 3.6.0"
-      )
+      clockWarning(Some(sourceInfo))
     }
     makePort(sourceInfo, idx, dir, clock)
   }
@@ -158,10 +165,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
     implicit compileOptions: CompileOptions
   ): Unit = {
     if (warn && clock != clockInst) {
-      Builder.warning(
-        "The clock used to initialize the memory is different than the one used to initialize the port. " +
-          "If this is intentional, please pass the clock explicitly when creating the port. This behavior will be an error in 3.6.0"
-      )
+      clockWarning(None)
     }
     implicit val sourceInfo = UnlocatableSourceInfo
     makePort(UnlocatableSourceInfo, idx, MemPortDirection.WRITE, clock) := data
@@ -220,10 +224,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
   ): Unit = {
     implicit val sourceInfo = UnlocatableSourceInfo
     if (warn && clock != clockInst) {
-      Builder.warning(
-        "The clock used to initialize the memory is different than the one used to initialize the port. " +
-          "If this is intentional, please pass the clock explicitly when creating the port. This behavior will be an error in 3.6.0"
-      )
+      clockWarning(None)
     }
     val accessor = makePort(sourceInfo, idx, MemPortDirection.WRITE, clock).asInstanceOf[Vec[Data]]
     val dataVec = data.asInstanceOf[Vec[Data]]
-- 
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