From 1321378dc8dd57066aa3efded39f40892295d757 Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Thu, 11 Jan 2024 12:06:43 -0800
Subject: Fix AbstractModule invocation

---
 core/src/main/scala/chisel3/AbstractModule.scala | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'core/src')

diff --git a/core/src/main/scala/chisel3/AbstractModule.scala b/core/src/main/scala/chisel3/AbstractModule.scala
index e054e537..7c4be632 100644
--- a/core/src/main/scala/chisel3/AbstractModule.scala
+++ b/core/src/main/scala/chisel3/AbstractModule.scala
@@ -10,13 +10,18 @@ import chisel3.internal.firrtl._
 import chisel3.experimental.BaseModule
 
 class AbstractInterface[T <: Data](params: T) {
+  println(params)
   val ioNode = IO(params)
 }
 
 /**
   A module that uses types from its metaconnects to type its IOs. 
   */
-class AbstractModule(iface: AbstractInterface[_]*) extends BaseModule {
+class AbstractModule(iface: Seq[AbstractInterface[_]]) extends BaseModule {
+  iface.foreach(x => {
+    println(x, x.ioNode)
+  })
+  println(iface)
   def generateComponent(): Option[chisel3.internal.firrtl.Component] = ???
   def initializeInParent(parentCompileOptions: chisel3.CompileOptions): Unit = ???
 }
-- 
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