From 7a3a5a07e9e340e11f8b7cb6a53c1f52f4e4d3a1 Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Tue, 2 Jan 2024 11:29:49 -0800
Subject: Add AbstractInterface and AbstractModule

---
 core/src/main/scala/chisel3/AbstractModule.scala | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 core/src/main/scala/chisel3/AbstractModule.scala

(limited to 'core/src/main')

diff --git a/core/src/main/scala/chisel3/AbstractModule.scala b/core/src/main/scala/chisel3/AbstractModule.scala
new file mode 100644
index 00000000..e054e537
--- /dev/null
+++ b/core/src/main/scala/chisel3/AbstractModule.scala
@@ -0,0 +1,22 @@
+package chisel3
+
+import scala.collection.immutable.ListMap
+import scala.collection.mutable.{ArrayBuffer, HashMap}
+import scala.language.experimental.macros
+
+import chisel3.internal._
+import chisel3.internal.Builder._
+import chisel3.internal.firrtl._
+import chisel3.experimental.BaseModule
+
+class AbstractInterface[T <: Data](params: T) {
+  val ioNode = IO(params)
+}
+
+/**
+  A module that uses types from its metaconnects to type its IOs. 
+  */
+class AbstractModule(iface: AbstractInterface[_]*) extends BaseModule {
+  def generateComponent(): Option[chisel3.internal.firrtl.Component] = ???
+  def initializeInParent(parentCompileOptions: chisel3.CompileOptions): Unit = ???
+}
-- 
cgit v1.2.3