From 0979133b2e67c82f916c2739bbda5df1c692a1d3 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Fri, 30 Oct 2020 09:57:30 -0700
Subject: Fix bug where refs may not get set for Records (#1645)

This requires a combination of things, but it happens to be a
combination used by Diplomacy in Rocket Chip. It must be a Record in
compatibility code with Vecs as fields and a mix of components with and
without set directions.---
 core/src/main/scala/chisel3/Aggregate.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'core/src/main')

diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala
index 6c11b2db..e45f5b46 100644
--- a/core/src/main/scala/chisel3/Aggregate.scala
+++ b/core/src/main/scala/chisel3/Aggregate.scala
@@ -493,7 +493,6 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio
   private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection): Unit = {
     try {
       super.bind(target, parentDirection)
-      setElementRefs()
     } catch {  // nasty compatibility mode shim, where anything flies
       case e: MixedDirectionAggregateException if !compileOptions.dontAssumeDirectionality =>
         val resolvedDirection = SpecifiedDirection.fromParent(parentDirection, specifiedDirection)
@@ -503,6 +502,7 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio
           case _ => ActualDirection.Bidirectional(ActualDirection.Default)
         }
     }
+    setElementRefs()
   }
 
   /** Creates a Bundle literal of this type with specified values. this must be a chisel type.
-- 
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