From bb3ef96d8911dbba4e22926ad4ce71eb8ab0d869 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Wed, 31 Aug 2022 01:41:09 +0000 Subject: Wires should have source location information in firrtl (#2714) (#2716) - Remove line defeating having wire locators `implicit val noSourceInfo = UnlocatableSourceInfo` from `WireDefault#apply` - Add test to show locators (cherry picked from commit f701a9f8151891e3bf9019cd3229cb3f2cd1833b) Co-authored-by: Chick Markley --- core/src/main/scala/chisel3/Data.scala | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'core/src/main/scala') diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala index d434735a..7c8ec1a9 100644 --- a/core/src/main/scala/chisel3/Data.scala +++ b/core/src/main/scala/chisel3/Data.scala @@ -9,7 +9,7 @@ import chisel3.experimental.{Analog, BaseModule, DataMirror, EnumType, FixedPoin import chisel3.internal.Builder.pushCommand import chisel3.internal._ import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.{DeprecatedSourceInfo, SourceInfo, SourceInfoTransform, UnlocatableSourceInfo} +import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform, UnlocatableSourceInfo} import scala.collection.immutable.LazyList // Needed for 2.12 alias import scala.reflect.ClassTag @@ -1075,7 +1075,6 @@ object WireDefault { implicit sourceInfo: SourceInfo, compileOptions: CompileOptions ): T = { - implicit val noSourceInfo = UnlocatableSourceInfo val x = Wire(t) requireIsHardware(init, "wire initializer") x := init -- cgit v1.2.3