From d1d38bd096fce8b92468720fbedc835ecda40e6b Mon Sep 17 00:00:00 2001
From: Kevin Laeufer
Date: Thu, 23 Sep 2021 11:12:26 -0700
Subject: make all verification statements publically available (#2089)

---
 core/src/main/scala/chisel3/internal/firrtl/Converter.scala | 4 ++--
 core/src/main/scala/chisel3/internal/firrtl/IR.scala        | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
index f56c3b15..1dc52823 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -142,8 +142,8 @@ private[chisel3] object Converter {
       Some(fir.IsInvalid(convert(info), convert(arg, ctx, info)))
     case e @ DefInstance(info, id, _) =>
       Some(fir.DefInstance(convert(info), e.name, id.name))
-    case Stop(info, clock, ret) =>
-      Some(fir.Stop(convert(info), ret, convert(clock, ctx, info), firrtl.Utils.one))
+    case e @ Stop(_, info, clock, ret) =>
+      Some(fir.Stop(convert(info), ret, convert(clock, ctx, info), firrtl.Utils.one, e.name))
     case e @ Printf(_, info, clock, pable) =>
       val (fmt, args) = unpack(pable, ctx)
       Some(fir.Print(convert(info), fir.StringLit(fmt),
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 0b568548..1a06cd36 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -784,7 +784,7 @@ case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
 case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command
 case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command
 case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
-case class Stop(sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Command
+case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition
 case class Port(id: Data, dir: SpecifiedDirection)
 case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition
 object Formal extends Enumeration {
@@ -792,7 +792,7 @@ object Formal extends Enumeration {
   val Assume = Value("assume")
   val Cover = Value("cover")
 }
-case class Verification[T <: BaseSim](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg,
+case class Verification[T <: VerificationStatement](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg,
                         predicate: Arg, message: String) extends Definition
 abstract class Component extends Arg {
   def id: BaseModule
-- 
cgit v1.2.3


From 790a1806c7c5333cea15abbd2657fa893beb92c9 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 5 Oct 2021 09:22:14 -0700
Subject: Remove v3.4.0 version of autoNameRecursively (#2149)

---
 .../main/scala/chisel3/internal/plugin/package.scala  | 19 -------------------
 1 file changed, 19 deletions(-)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/plugin/package.scala b/core/src/main/scala/chisel3/internal/plugin/package.scala
index c17baf22..9b9b41cd 100644
--- a/core/src/main/scala/chisel3/internal/plugin/package.scala
+++ b/core/src/main/scala/chisel3/internal/plugin/package.scala
@@ -3,27 +3,8 @@
 package chisel3.internal
 
 package object plugin {
-  /** Used by Chisel's compiler plugin to automatically name signals
-    * DO NOT USE in your normal Chisel code!!!
-    *
-    * @param name The name to use
-    * @param nameMe The thing to be named
-    * @tparam T The type of the thing to be named
-    * @return The thing, but now named
-    * @note This is the version called by chisel3-plugin prior to v3.4.1
-    */
-  def autoNameRecursively[T <: Any](name: String, nameMe: T): T = {
-    chisel3.internal.Builder.nameRecursively(
-      name.replace(" ", ""),
-      nameMe,
-      (id: chisel3.internal.HasId, n: String) => id.autoSeed(n)
-    )
-    nameMe
-  }
 
   // The actual implementation
-  // Cannot be unified with (String, T) => T (v3.4.0 version) because of special behavior of ports
-  // in .autoSeed
   private def _autoNameRecursively[T <: Any](prevId: Long, name: String, nameMe: T): T = {
     chisel3.internal.Builder.nameRecursively(
       name,
-- 
cgit v1.2.3


From 110705eeace4f9165dc6377e55c86a599f37a465 Mon Sep 17 00:00:00 2001
From: Jared Barocsi
Date: Tue, 5 Oct 2021 12:33:23 -0700
Subject: Deprecate auto-application of empty argument lists to parameterless
 functions (#2124)

* Migrate nullary funcs to parameterless versions
* Make deprecation message and dummy arguments clear and consistent

Co-authored-by: Megan Wachs <megan@sifive.com>---
 core/src/main/scala/chisel3/internal/Builder.scala | 12 ++++++------
 core/src/main/scala/chisel3/internal/prefix.scala  |  4 ++--
 2 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index 441abc92..4e68623d 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -105,7 +105,7 @@ private[chisel3] trait HasId extends InstanceId {
   private var auto_seed: Option[String] = None
 
   // Prefix at time when this class is constructed
-  private val construction_prefix: Prefix = Builder.getPrefix()
+  private val construction_prefix: Prefix = Builder.getPrefix
 
   // Prefix when the latest [[suggestSeed]] or [[autoSeed]] is called
   private var prefix_seed: Prefix = Nil
@@ -133,7 +133,7 @@ private[chisel3] trait HasId extends InstanceId {
   private[chisel3] def forceAutoSeed(seed: String): this.type = {
     auto_seed = Some(seed)
     for(hook <- auto_postseed_hooks) { hook(seed) }
-    prefix_seed = Builder.getPrefix()
+    prefix_seed = Builder.getPrefix
     this
   }
 
@@ -149,7 +149,7 @@ private[chisel3] trait HasId extends InstanceId {
     */
   def suggestName(seed: =>String): this.type = {
     if(suggested_seed.isEmpty) suggested_seed = Some(seed)
-    prefix_seed = Builder.getPrefix()
+    prefix_seed = Builder.getPrefix
     for(hook <- suggest_postseed_hooks) { hook(seed) }
     this
   }
@@ -485,7 +485,7 @@ private[chisel3] object Builder extends LazyLogging {
   }
 
   // Returns the prefix stack at this moment
-  def getPrefix(): Prefix = chiselContext.get().prefixStack
+  def getPrefix: Prefix = chiselContext.get().prefixStack
 
   def currentModule: Option[BaseModule] = dynamicContextVar.value match {
     case Some(dyanmicContext) => dynamicContext.currentModule
@@ -572,7 +572,7 @@ private[chisel3] object Builder extends LazyLogging {
     dynamicContext.whenStack = s
   }
 
-  def currentWhen(): Option[WhenContext] = dynamicContext.whenStack.headOption
+  def currentWhen: Option[WhenContext] = dynamicContext.whenStack.headOption
 
   def currentClock: Option[Clock] = dynamicContext.currentClock
   def currentClock_=(newClock: Option[Clock]): Unit = {
@@ -615,7 +615,7 @@ private[chisel3] object Builder extends LazyLogging {
   }
   def pushOp[T <: Data](cmd: DefPrim[T]): T = {
     // Bind each element of the returned Data to being a Op
-    cmd.id.bind(OpBinding(forcedUserModule, currentWhen()))
+    cmd.id.bind(OpBinding(forcedUserModule, currentWhen))
     pushCommand(cmd).id
   }
 
diff --git a/core/src/main/scala/chisel3/internal/prefix.scala b/core/src/main/scala/chisel3/internal/prefix.scala
index 9dc14901..620d0864 100644
--- a/core/src/main/scala/chisel3/internal/prefix.scala
+++ b/core/src/main/scala/chisel3/internal/prefix.scala
@@ -51,7 +51,7 @@ private[chisel3] object prefix { // scalastyle:ignore
     // This causes extra prefixes to be added, and subsequently cleared in the
     // Module constructor. Thus, we need to just make sure if the previous push
     // was an incorrect one, to not pop off an empty stack
-    if(Builder.getPrefix().nonEmpty) Builder.popPrefix()
+    if(Builder.getPrefix.nonEmpty) Builder.popPrefix()
     ret
   }
 }
@@ -77,7 +77,7 @@ private[chisel3] object noPrefix {
     * @return The return value of the provided function
     */
   def apply[T](f: => T): T = {
-    val prefix = Builder.getPrefix()
+    val prefix = Builder.getPrefix
     Builder.clearPrefix()
     val ret = f
     Builder.setPrefix(prefix)
-- 
cgit v1.2.3


From c2985aa6ef95a45d6ce9663a17f835eaba0cb9c5 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 5 Oct 2021 13:20:28 -0700
Subject: Fix naming of unwrapped val io in Chisel.Modules (#2150)

The removal of virtual method io accidentally made the naming of io in
compatibility mode Bundles sensitive to the prefix at the time of the
first access of the field. It also made .suggestName able to override
the name. This commit fixes that issue by forcing the name of the io
Data to be "io" no matter what.---
 core/src/main/scala/chisel3/internal/Builder.scala | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index 4e68623d..0a0a3f2d 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -154,6 +154,17 @@ private[chisel3] trait HasId extends InstanceId {
     this
   }
 
+  // Internal version of .suggestName that can override a user-suggested name
+  // This only exists for maintaining "val io" naming in compatibility-mode Modules without IO
+  // wrapping
+  private[chisel3] def forceFinalName(seed: String): this.type = {
+    // This could be called with user prefixes, ignore them
+    noPrefix {
+      suggested_seed = Some(seed)
+      this.suggestName(seed)
+    }
+  }
+
   /** Computes the name of this HasId, if one exists
     * @param defaultPrefix Optionally provide a default prefix for computing the name
     * @param defaultSeed Optionally provide default seed for computing the name
-- 
cgit v1.2.3


From d6907893f019ee86573dc81768884150e541dba3 Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Wed, 20 Oct 2021 00:13:34 -0400
Subject: Update computeName and callsites (#2192)

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 core/src/main/scala/chisel3/internal/Builder.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index 0a0a3f2d..57e7578a 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -170,7 +170,7 @@ private[chisel3] trait HasId extends InstanceId {
     * @param defaultSeed Optionally provide default seed for computing the name
     * @return the name, if it can be computed
     */
-  def computeName(defaultPrefix: Option[String], defaultSeed: Option[String]): Option[String] = {
+  private[chisel3] def _computeName(defaultPrefix: Option[String], defaultSeed: Option[String]): Option[String] = {
     /** Computes a name of this signal, given the seed and prefix
       * @param seed
       * @param prefix
@@ -214,7 +214,7 @@ private[chisel3] trait HasId extends InstanceId {
   // (e.g. tried to suggest a name to part of a Record)
   private[chisel3] def forceName(prefix: Option[String], default: =>String, namespace: Namespace): Unit =
     if(_ref.isEmpty) {
-      val candidate_name = computeName(prefix, Some(default)).get
+      val candidate_name = _computeName(prefix, Some(default)).get
       val available_name = namespace.name(candidate_name)
       setRef(Ref(available_name))
     }
@@ -234,7 +234,7 @@ private[chisel3] trait HasId extends InstanceId {
 
   private def refName(c: Component): String = _ref match {
     case Some(arg) => arg fullName c
-    case None => computeName(None, None).get
+    case None => _computeName(None, None).get
   }
 
   // Helper for reifying views if they map to a single Target
-- 
cgit v1.2.3


From ef8a9c2148f01e058d2986c9d64f0c35f640790c Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Wed, 27 Oct 2021 16:52:56 -0700
Subject: Add Select APIs for Hierarchy package (#2210)

* Add Hierarchy trait

* Add Hierarchy trait

* Add Hierarchy scaladoc

* Add license

* Add isA and tests

* Add back isA

* Add new Select APIs for hierarchy package

* Update scaladoc

* Write outlines for tests

* Add tests and fixes to new Select functions

* Make calculate via lazy val

* Apply suggestions from code review

Co-authored-by: Megan Wachs <megan@sifive.com>

* Apply suggestions from code review

Co-authored-by: Megan Wachs <megan@sifive.com>

* Clean up scaladoc

* Add shouldNot compile

* Apply suggestions from code review

Co-authored-by: Megan Wachs <megan@sifive.com>

* Bugfix all funcs should analyze root too

* Add mdoc, bugfix toDefinition

* Make func private, add scaladoc

* Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Made protected vals private

* Apply suggestions from code review

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Address code review comments

* Added additional null check

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>---
 core/src/main/scala/chisel3/internal/Builder.scala | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index 57e7578a..3761b371 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -561,6 +561,8 @@ private[chisel3] object Builder extends LazyLogging {
       // A bare api call is, e.g. calling Wire() from the scala console).
     )
   }
+  def hasDynamicContext: Boolean = dynamicContextVar.value.isDefined
+
   def readyForModuleConstr: Boolean = dynamicContext.readyForModuleConstr
   def readyForModuleConstr_=(target: Boolean): Unit = {
     dynamicContext.readyForModuleConstr = target
-- 
cgit v1.2.3


From 0c43dadf60c1485be348115c20690990f0fea940 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Thu, 28 Oct 2021 18:18:34 -0700
Subject: Exposing more APIs from D/I internals (#2220)

Exposing more internals of D/I, which are required for supporting D/I with more powerful Chisel libraries:

- Exposing IsClone[_]
- Exposing InstantiableClone[_]
- Gated builders for Instance/Definition
- Unsealing Lookupable, with protected accessors for proto and cloned---
 core/src/main/scala/chisel3/internal/Builder.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index 3761b371..55f89ae7 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -6,7 +6,7 @@ import scala.util.DynamicVariable
 import scala.collection.mutable.ArrayBuffer
 import chisel3._
 import chisel3.experimental._
-import chisel3.experimental.hierarchy.Instance
+import chisel3.experimental.hierarchy.{Instance, Clone}
 import chisel3.internal.firrtl._
 import chisel3.internal.naming._
 import _root_.firrtl.annotations.{CircuitName, ComponentName, IsMember, ModuleName, Named, ReferenceTarget}
@@ -672,8 +672,8 @@ private[chisel3] object Builder extends LazyLogging {
     * (Note: Map is Iterable[Tuple2[_,_]] and thus excluded)
     */
   def nameRecursively(prefix: String, nameMe: Any, namer: (HasId, String) => Unit): Unit = nameMe match {
-    case (id: Instance[_]) => id.cloned match {
-      case Right(m: internal.BaseModule.ModuleClone[_]) => namer(m.getPorts, prefix)
+    case (id: Instance[_]) => id.underlying match {
+      case Clone(m: internal.BaseModule.ModuleClone[_]) => namer(m.getPorts, prefix)
       case _ =>
     }
     case (id: HasId) => namer(id, prefix)
-- 
cgit v1.2.3


From a476329ef7b051aa480903cacd7d62ee46980c84 Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Tue, 30 Nov 2021 17:45:59 -0800
Subject: Bugfix - definition name index skipping with D/I (#2249)

* Bugfix - definition name index skipping with D/I

* Add tests to DefinitionSpec

* Add failing test

* Fix failing test

* Update core/src/main/scala/chisel3/internal/Builder.scala

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>

* whitespace

* revert package private val

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>---
 core/src/main/scala/chisel3/internal/Builder.scala | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index 55f89ae7..966e60d6 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -740,14 +740,16 @@ private[chisel3] object Builder extends LazyLogging {
     renames
   }
 
-  private [chisel3] def build[T <: BaseModule](f: => T, dynamicContext: DynamicContext): (Circuit, T) = {
+  private[chisel3] def build[T <: BaseModule](f: => T, dynamicContext: DynamicContext, forceModName: Boolean = true): (Circuit, T) = {
     dynamicContextVar.withValue(Some(dynamicContext)) {
       ViewParent // Must initialize the singleton in a Builder context or weird things can happen
                  // in tiny designs/testcases that never access anything in chisel3.internal
       checkScalaVersion()
       logger.info("Elaborating design...")
       val mod = f
-      mod.forceName(None, mod.name, globalNamespace)
+      if (forceModName) { // This avoids definition name index skipping with D/I
+        mod.forceName(None, mod.name, globalNamespace)
+      }
       errors.checkpoint(logger)
       logger.info("Done elaborating.")
 
-- 
cgit v1.2.3


From 392ea3c9b5b04e374eeb1bf3b0d87ac9fbf45513 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 1 Dec 2021 14:49:34 -0800
Subject: Require the chisel3 compiler plugin (#2271)

As the chisel3 compiler plugin is now required, we can delete unused
code for reflective autoclonetype as well as the noPluginTests.---
 core/src/main/scala/chisel3/internal/Builder.scala | 49 ----------------------
 1 file changed, 49 deletions(-)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index 966e60d6..71894887 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -343,9 +343,6 @@ private[chisel3] trait NamedComponent extends HasId {
 private[chisel3] class ChiselContext() {
   val idGen = new IdGen
 
-  // Record the Bundle instance, class name, method name, and reverse stack trace position of open Bundles
-  val bundleStack: ArrayBuffer[(Bundle, String, String, Int)] = ArrayBuffer()
-
   // Records the different prefixes which have been scoped at this point in time
   var prefixStack: Prefix = Nil
 
@@ -360,8 +357,6 @@ private[chisel3] class DynamicContext(val annotationSeq: AnnotationSeq) {
   val components = ArrayBuffer[Component]()
   val annotations = ArrayBuffer[ChiselAnnotation]()
   var currentModule: Option[BaseModule] = None
-  // This is only used for testing, it can be removed if the plugin becomes mandatory
-  var allowReflectiveAutoCloneType = true
 
   /** Contains a mapping from a elaborated module to their aspect
     * Set by [[ModuleAspect]]
@@ -603,16 +598,6 @@ private[chisel3] object Builder extends LazyLogging {
                      .getOrElse(false)
   }
 
-  // This should only be used for testing, must be true outside of Builder context
-  def allowReflectiveAutoCloneType: Boolean = {
-    dynamicContextVar.value
-                     .map(_.allowReflectiveAutoCloneType)
-                     .getOrElse(true)
-  }
-  def allowReflectiveAutoCloneType_=(value: Boolean): Unit = {
-    dynamicContext.allowReflectiveAutoCloneType = value
-  }
-
   def forcedClock: Clock = currentClock.getOrElse(
     throwException("Error: No implicit clock.")
   )
@@ -632,40 +617,6 @@ private[chisel3] object Builder extends LazyLogging {
     pushCommand(cmd).id
   }
 
-  // Called when Bundle construction begins, used to record a stack of open Bundle constructors to
-  // record candidates for Bundle autoclonetype. This is a best-effort guess.
-  // Returns the current stack of open Bundles
-  // Note: elt will NOT have finished construction, its elements cannot be accessed
-  def updateBundleStack(elt: Bundle): Seq[Bundle] = {
-    val stackElts = Thread.currentThread().getStackTrace()
-        .reverse  // so stack frame numbers are deterministic across calls
-        .dropRight(2)  // discard Thread.getStackTrace and updateBundleStack
-
-    // Determine where we are in the Bundle stack
-    val eltClassName = elt.getClass.getName
-    val eltStackPos = stackElts.map(_.getClassName).lastIndexOf(eltClassName)
-
-    // Prune the existing Bundle stack of closed Bundles
-    // If we know where we are in the stack, discard frames above that
-    val stackEltsTop = if (eltStackPos >= 0) eltStackPos else stackElts.size
-    val pruneLength = chiselContext.get.bundleStack.reverse.prefixLength { case (_, cname, mname, pos) =>
-      pos >= stackEltsTop || stackElts(pos).getClassName != cname || stackElts(pos).getMethodName != mname
-    }
-    chiselContext.get.bundleStack.trimEnd(pruneLength)
-
-    // Return the stack state before adding the most recent bundle
-    val lastStack = chiselContext.get.bundleStack.map(_._1).toSeq
-
-    // Append the current Bundle to the stack, if it's on the stack trace
-    if (eltStackPos >= 0) {
-      val stackElt = stackElts(eltStackPos)
-      chiselContext.get.bundleStack.append((elt, eltClassName, stackElt.getMethodName, eltStackPos))
-    }
-    // Otherwise discard the stack frame, this shouldn't fail noisily
-
-    lastStack
-  }
-
   /** Recursively suggests names to supported "container" classes
     * Arbitrary nestings of supported classes are allowed so long as the
     * innermost element is of type HasId
-- 
cgit v1.2.3


From 9dfee489b15642745174d191181ebf6f570db3ca Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Wed, 1 Dec 2021 16:09:34 -0800
Subject: Refactor Data.toString (#2197)

Provides a more intuitive implementation of toString for Data.
Utilizes the fact that the compiler plugin provides names earlier than
Chisel had in the past so we can accurately guess the name of
signals even in the currently elaborating module.

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>---
 core/src/main/scala/chisel3/internal/firrtl/IR.scala | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 1a06cd36..a352c96a 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -86,6 +86,19 @@ case class Node(id: HasId) extends Arg {
   }
 }
 
+private[chisel3] object Arg {
+  def earlyLocalName(id: HasId): String = id.getOptionRef match {
+    case Some(Index(Node(imm), Node(value))) => s"${earlyLocalName(imm)}[${earlyLocalName(imm)}]"
+    case Some(Index(Node(imm), arg)) => s"${earlyLocalName(imm)}[${arg.localName}]"
+    case Some(Slot(Node(imm), name)) => s"${earlyLocalName(imm)}.$name"
+    case Some(arg) => arg.name
+    case None => id match {
+      case data: Data => data._computeName(None, Some("?")).get
+      case _ => "?"
+    }
+  }
+}
+
 abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
   private[chisel3] def forcedWidth = widthArg.known
   private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
@@ -196,7 +209,7 @@ case class Slot(imm: Node, name: String) extends Arg {
     if (immName.isEmpty) name else s"$immName.$name"
   }
 }
-case class Index(imm: Arg, value: Arg) extends Arg {
+case class Index(imm: Node, value: Arg) extends Arg {
   def name: String = s"[$value]"
   override def contextualName(ctx: Component): String = s"${imm.contextualName(ctx)}[${value.contextualName(ctx)}]"
   override def localName: String = s"${imm.localName}[${value.localName}]"
-- 
cgit v1.2.3


From 3f21bbb52363c3105f6a0ff961fa7a411dd0c7ab Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Thu, 9 Dec 2021 11:19:27 -0800
Subject: Better MonoConnect error messages (#2248)

Co-authored-by: Megan Wachs <megan@sifive.com>---
 .../main/scala/chisel3/internal/MonoConnect.scala  | 72 +++++++++++-----------
 1 file changed, 37 insertions(+), 35 deletions(-)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/MonoConnect.scala b/core/src/main/scala/chisel3/internal/MonoConnect.scala
index 5cbab329..6173fc91 100644
--- a/core/src/main/scala/chisel3/internal/MonoConnect.scala
+++ b/core/src/main/scala/chisel3/internal/MonoConnect.scala
@@ -36,33 +36,35 @@ import chisel3.internal.sourceinfo.SourceInfo
 */
 
 private[chisel3] object MonoConnect {
+  def formatName(data: Data) = s"""${data.earlyName} in ${data.parentNameOpt.getOrElse("(unknown)")}"""
+
   // These are all the possible exceptions that can be thrown.
   // These are from element-level connection
-  def UnreadableSourceException =
-    MonoConnectException(": Source is unreadable from current module.")
-  def UnwritableSinkException =
-    MonoConnectException(": Sink is unwriteable by current module.")
-  def SourceEscapedWhenScopeException =
-    MonoConnectException(": Source has escaped the scope of the when in which it was constructed.")
-  def SinkEscapedWhenScopeException =
-    MonoConnectException(": Sink has escaped the scope of the when in which it was constructed.")
+  def UnreadableSourceException(sink: Data, source: Data) =
+    MonoConnectException(s"""${formatName(source)} cannot be read from module ${sink.parentNameOpt.getOrElse("(unknown)")}.""")
+  def UnwritableSinkException(sink: Data, source: Data) =
+    MonoConnectException(s"""${formatName(sink)} cannot be written from module ${source.parentNameOpt.getOrElse("(unknown)")}.""")
+  def SourceEscapedWhenScopeException(source: Data) =
+    MonoConnectException(s"Source ${formatName(source)} has escaped the scope of the when in which it was constructed.")
+  def SinkEscapedWhenScopeException(sink: Data) =
+    MonoConnectException(s"Sink ${formatName(sink)} has escaped the scope of the when in which it was constructed.")
   def UnknownRelationException =
-    MonoConnectException(": Sink or source unavailable to current module.")
+    MonoConnectException("Sink or source unavailable to current module.")
   // These are when recursing down aggregate types
   def MismatchedVecException =
-    MonoConnectException(": Sink and Source are different length Vecs.")
+    MonoConnectException("Sink and Source are different length Vecs.")
   def MissingFieldException(field: String) =
-    MonoConnectException(s": Source Record missing field ($field).")
-  def MismatchedException(sink: String, source: String) =
-    MonoConnectException(s": Sink ($sink) and Source ($source) have different types.")
+    MonoConnectException(s"Source Record missing field ($field).")
+  def MismatchedException(sink: Data, source: Data) =
+    MonoConnectException(s"Sink (${sink.cloneType.toString}) and Source (${source.cloneType.toString}) have different types.")
   def DontCareCantBeSink =
-    MonoConnectException(": DontCare cannot be a connection sink (LHS)")
-  def AnalogCantBeMonoSink =
-    MonoConnectException(": Analog cannot participate in a mono connection (sink - LHS)")
-  def AnalogCantBeMonoSource =
-    MonoConnectException(": Analog cannot participate in a mono connection (source - RHS)")
-  def AnalogMonoConnectionException =
-    MonoConnectException(": Analog cannot participate in a mono connection (source and sink)")
+    MonoConnectException("DontCare cannot be a connection sink")
+  def AnalogCantBeMonoSink(sink: Data) =
+    MonoConnectException(s"Sink ${formatName(sink)} of type Analog cannot participate in a mono connection (:=)")
+  def AnalogCantBeMonoSource(source: Data) =
+    MonoConnectException(s"Source ${formatName(source)} of type Analog cannot participate in a mono connection (:=)")
+  def AnalogMonoConnectionException(source: Data, sink: Data) =
+    MonoConnectException(s"Source ${formatName(source)} and sink ${formatName(sink)} of type Analog cannot participate in a mono connection (:=)")
 
   def checkWhenVisibility(x: Data): Boolean = {
     x.topBinding match {
@@ -169,13 +171,13 @@ private[chisel3] object MonoConnect {
       // DontCare as a sink is illegal.
       case (DontCare, _) => throw DontCareCantBeSink
       // Analog is illegal in mono connections.
-      case (_: Analog, _:Analog) => throw AnalogMonoConnectionException
+      case (_: Analog, _:Analog) => throw AnalogMonoConnectionException(source, sink)
       // Analog is illegal in mono connections.
-      case (_: Analog, _) => throw AnalogCantBeMonoSink
+      case (_: Analog, _) => throw AnalogCantBeMonoSink(sink)
       // Analog is illegal in mono connections.
-      case (_, _: Analog) => throw AnalogCantBeMonoSource
+      case (_, _: Analog) => throw AnalogCantBeMonoSource(source)
       // Sink and source are different subtypes of data so fail
-      case (sink, source) => throw MismatchedException(sink.toString, source.toString)
+      case (sink, source) => throw MismatchedException(sink, source)
     }
 
   // This function (finally) issues the connection operation
@@ -196,7 +198,7 @@ private[chisel3] object MonoConnect {
     val source = reify(_source)
     // If source has no location, assume in context module
     // This can occur if is a literal, unbound will error previously
-    val sink_mod: BaseModule   = sink.topBinding.location.getOrElse(throw UnwritableSinkException)
+    val sink_mod: BaseModule   = sink.topBinding.location.getOrElse(throw UnwritableSinkException(sink, source))
     val source_mod: BaseModule = source.topBinding.location.getOrElse(context_mod)
 
     val sink_parent = Builder.retrieveParent(sink_mod, context_mod).getOrElse(None)
@@ -206,11 +208,11 @@ private[chisel3] object MonoConnect {
     val source_direction = BindingDirection.from(source.topBinding, source.direction)
 
     if (!checkWhenVisibility(sink)) {
-      throw SinkEscapedWhenScopeException
+      throw SinkEscapedWhenScopeException(sink)
     }
 
     if (!checkWhenVisibility(source)) {
-      throw SourceEscapedWhenScopeException
+      throw SourceEscapedWhenScopeException(source)
     }
 
     // CASE: Context is same module that both left node and right node are in
@@ -220,7 +222,7 @@ private[chisel3] object MonoConnect {
         //    CURRENT MOD   CURRENT MOD
         case (Output,       _) => issueConnect(sink, source)
         case (Internal,     _) => issueConnect(sink, source)
-        case (Input,        _) => throw UnwritableSinkException
+        case (Input,        _) => throw UnwritableSinkException(sink, source)
       }
     }
 
@@ -238,11 +240,11 @@ private[chisel3] object MonoConnect {
           if (!(connectCompileOptions.dontAssumeDirectionality)) {
             issueConnect(sink, source)
           } else {
-            throw UnreadableSourceException
+            throw UnreadableSourceException(sink, source)
           }
         }
         case (Input,        Output) if (!(connectCompileOptions.dontTryConnectionsSwapped)) => issueConnect(source, sink)
-        case (Input,        _)    => throw UnwritableSinkException
+        case (Input,        _)    => throw UnwritableSinkException(sink, source)
       }
     }
 
@@ -253,8 +255,8 @@ private[chisel3] object MonoConnect {
         //    SINK          SOURCE
         //    CHILD MOD     CURRENT MOD
         case (Input,        _) => issueConnect(sink, source)
-        case (Output,       _) => throw UnwritableSinkException
-        case (Internal,     _) => throw UnwritableSinkException
+        case (Output,       _) => throw UnwritableSinkException(sink, source)
+        case (Internal,     _) => throw UnwritableSinkException(sink, source)
       }
     }
 
@@ -268,15 +270,15 @@ private[chisel3] object MonoConnect {
         //    CHILD MOD     CHILD MOD
         case (Input,        Input)  => issueConnect(sink, source)
         case (Input,        Output) => issueConnect(sink, source)
-        case (Output,       _)      => throw UnwritableSinkException
+        case (Output,       _)      => throw UnwritableSinkException(sink, source)
         case (_,            Internal) => {
           if (!(connectCompileOptions.dontAssumeDirectionality)) {
             issueConnect(sink, source)
           } else {
-            throw UnreadableSourceException
+            throw UnreadableSourceException(sink, source)
           }
         }
-        case (Internal,     _)      => throw UnwritableSinkException
+        case (Internal,     _)      => throw UnwritableSinkException(sink, source)
       }
     }
 
-- 
cgit v1.2.3


From 21e324727e99f0bc124aaddea7fe294b4111c23a Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Tue, 14 Dec 2021 09:41:47 -0800
Subject: Make stuff in IR.scala package private (#2274)

---
 .../main/scala/chisel3/internal/firrtl/IR.scala    | 85 +++++++++++-----------
 1 file changed, 43 insertions(+), 42 deletions(-)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index a352c96a..3279e9b9 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -15,11 +15,11 @@ import scala.collection.immutable.NumericRange
 import scala.math.BigDecimal.RoundingMode
 
 
-case class PrimOp(name: String) {
+private[chisel3] case class PrimOp(name: String) {
   override def toString: String = name
 }
 
-object PrimOp {
+private[chisel3] object PrimOp {
   val AddOp = PrimOp("add")
   val SubOp = PrimOp("sub")
   val TailOp = PrimOp("tail")
@@ -64,14 +64,14 @@ object PrimOp {
   val AsAsyncResetOp = PrimOp("asAsyncReset")
 }
 
-abstract class Arg {
+sealed private[chisel3] abstract class Arg {
   def localName: String = name
   def contextualName(ctx: Component): String = name
   def fullName(ctx: Component): String = contextualName(ctx)
   def name: String
 }
 
-case class Node(id: HasId) extends Arg {
+private[chisel3] case class Node(id: HasId) extends Arg {
   override def contextualName(ctx: Component): String = id.getOptionRef match {
     case Some(arg) => arg.contextualName(ctx)
     case None => id.instanceName
@@ -99,7 +99,7 @@ private[chisel3] object Arg {
   }
 }
 
-abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
+private[chisel3] abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
   private[chisel3] def forcedWidth = widthArg.known
   private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
   override def contextualName(ctx: Component): String = name
@@ -125,11 +125,11 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
   }
 }
 
-case class ILit(n: BigInt) extends Arg {
+private[chisel3] case class ILit(n: BigInt) extends Arg {
   def name: String = n.toString
 }
 
-case class ULit(n: BigInt, w: Width) extends LitArg(n, w) {
+private[chisel3] case class ULit(n: BigInt, w: Width) extends LitArg(n, w) {
   def name: String = "UInt" + width + "(\"h0" + num.toString(16) + "\")"
   def minWidth: Int = 1 max n.bitLength
 
@@ -140,7 +140,7 @@ case class ULit(n: BigInt, w: Width) extends LitArg(n, w) {
   require(n >= 0, s"UInt literal ${n} is negative")
 }
 
-case class SLit(n: BigInt, w: Width) extends LitArg(n, w) {
+private[chisel3] case class SLit(n: BigInt, w: Width) extends LitArg(n, w) {
   def name: String = {
     val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n
     s"asSInt(${ULit(unsigned, width).name})"
@@ -152,7 +152,7 @@ case class SLit(n: BigInt, w: Width) extends LitArg(n, w) {
   }
 }
 
-case class FPLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) {
+private[chisel3] case class FPLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) {
   def name: String = {
     val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n
     s"asFixedPoint(${ULit(unsigned, width).name}, ${binaryPoint.asInstanceOf[KnownBinaryPoint].value})"
@@ -164,7 +164,7 @@ case class FPLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n
   }
 }
 
-case class IntervalLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) {
+private[chisel3] case class IntervalLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) {
   def name: String = {
     val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n
     s"asInterval(${ULit(unsigned, width).name}, ${n}, ${n}, ${binaryPoint.asInstanceOf[KnownBinaryPoint].value})"
@@ -180,12 +180,12 @@ case class IntervalLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends Li
   }
 }
 
-case class Ref(name: String) extends Arg
+private[chisel3] case class Ref(name: String) extends Arg
 /** Arg for ports of Modules
   * @param mod the module this port belongs to
   * @param name the name of the port
   */
-case class ModuleIO(mod: BaseModule, name: String) extends Arg {
+private[chisel3] case class ModuleIO(mod: BaseModule, name: String) extends Arg {
   override def contextualName(ctx: Component): String =
     if (mod eq ctx.id) name else s"${mod.getRef.name}.$name"
 }
@@ -193,13 +193,13 @@ case class ModuleIO(mod: BaseModule, name: String) extends Arg {
   * @param mod The original module for which these ports are a clone
   * @param name the name of the module instance
   */
-case class ModuleCloneIO(mod: BaseModule, name: String) extends Arg {
+private[chisel3] case class ModuleCloneIO(mod: BaseModule, name: String) extends Arg {
   override def localName = ""
   override def contextualName(ctx: Component): String =
     // NOTE: mod eq ctx.id only occurs in Target and Named-related APIs
     if (mod eq ctx.id) localName else name
 }
-case class Slot(imm: Node, name: String) extends Arg {
+private[chisel3] case class Slot(imm: Node, name: String) extends Arg {
   override def contextualName(ctx: Component): String = {
     val immName = imm.contextualName(ctx)
     if (immName.isEmpty) name else s"$immName.$name"
@@ -209,7 +209,8 @@ case class Slot(imm: Node, name: String) extends Arg {
     if (immName.isEmpty) name else s"$immName.$name"
   }
 }
-case class Index(imm: Node, value: Arg) extends Arg {
+
+private[chisel3] case class Index(imm: Arg, value: Arg) extends Arg {
   def name: String = s"[$value]"
   override def contextualName(ctx: Component): String = s"${imm.contextualName(ctx)}[${value.contextualName(ctx)}]"
   override def localName: String = s"${imm.localName}[${value.localName}]"
@@ -773,47 +774,47 @@ sealed class IntervalRange(
   }
 }
 
-abstract class Command {
+private[chisel3] abstract class Command {
   def sourceInfo: SourceInfo
 }
-abstract class Definition extends Command {
+private[chisel3] abstract class Definition extends Command {
   def id: HasId
   def name: String = id.getRef.name
 }
-case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition
-case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command
-case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition
-case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition
-case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
-case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition
-case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition
-case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition
-case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition
-case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command
-case class WhenEnd(sourceInfo: SourceInfo, firrtlDepth: Int, hasAlt: Boolean = false) extends Command
-case class AltBegin(sourceInfo: SourceInfo) extends Command
-case class OtherwiseEnd(sourceInfo: SourceInfo, firrtlDepth: Int) extends Command
-case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
-case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command
-case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command
-case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
-case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition
-case class Port(id: Data, dir: SpecifiedDirection)
-case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition
-object Formal extends Enumeration {
+private[chisel3] case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition
+private[chisel3] case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command
+private[chisel3] case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition
+private[chisel3] case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition
+private[chisel3] case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
+private[chisel3] case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition
+private[chisel3] case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition
+private[chisel3] case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition
+private[chisel3] case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition
+private[chisel3] case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command
+private[chisel3] case class WhenEnd(sourceInfo: SourceInfo, firrtlDepth: Int, hasAlt: Boolean = false) extends Command
+private[chisel3] case class AltBegin(sourceInfo: SourceInfo) extends Command
+private[chisel3] case class OtherwiseEnd(sourceInfo: SourceInfo, firrtlDepth: Int) extends Command
+private[chisel3] case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
+private[chisel3] case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command
+private[chisel3] case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command
+private[chisel3] case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
+private[chisel3] case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition
+private[chisel3] case class Port(id: Data, dir: SpecifiedDirection)
+private[chisel3] case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition
+private[chisel3] object Formal extends Enumeration {
   val Assert = Value("assert")
   val Assume = Value("assume")
   val Cover = Value("cover")
 }
-case class Verification[T <: VerificationStatement](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg,
+private[chisel3] case class Verification[T <: VerificationStatement](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg,
                         predicate: Arg, message: String) extends Definition
-abstract class Component extends Arg {
+private[chisel3] abstract class Component extends Arg {
   def id: BaseModule
   def name: String
   def ports: Seq[Port]
 }
-case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
-case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component
+private[chisel3] case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
+private[chisel3] case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component
 
 case class Circuit(name: String, components: Seq[Component], annotations: Seq[ChiselAnnotation], renames: RenameMap) {
   def firrtlAnnotations: Iterable[Annotation] = annotations.flatMap(_.toFirrtl.update(renames))
-- 
cgit v1.2.3


From 4ff431bb5c7978c9915bcd6080a4f27ef12ae607 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 15 Dec 2021 13:02:12 -0800
Subject: Restore Port to public API and deprecate (#2302)

Also clean up deprecation warnings for replacement APIs and add
clarifying ScalaDoc.---
 core/src/main/scala/chisel3/internal/firrtl/Converter.scala | 3 ++-
 core/src/main/scala/chisel3/internal/firrtl/IR.scala        | 9 ++++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
index 1dc52823..ac784882 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -7,10 +7,11 @@ import chisel3.internal.sourceinfo.{NoSourceInfo, SourceInfo, SourceLine, Unloca
 import firrtl.{ir => fir}
 import chisel3.internal.{HasId, castToInt, throwException}
 
-import scala.annotation.tailrec
+import scala.annotation.{nowarn, tailrec}
 import scala.collection.immutable.Queue
 import scala.collection.immutable.LazyList // Needed for 2.12 alias
 
+@nowarn("msg=class Port") // delete when Port becomes private
 private[chisel3] object Converter {
   // TODO modeled on unpack method on Printable, refactor?
   def unpack(pable: Printable, ctx: Component): (String, Seq[Arg]) = pable match {
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 3279e9b9..e3ea42c3 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -13,6 +13,7 @@ import _root_.firrtl.annotations.Annotation
 
 import scala.collection.immutable.NumericRange
 import scala.math.BigDecimal.RoundingMode
+import scala.annotation.nowarn
 
 
 private[chisel3] case class PrimOp(name: String) {
@@ -789,6 +790,7 @@ private[chisel3] case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock:
 private[chisel3] case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition
 private[chisel3] case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition
 private[chisel3] case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition
+@nowarn("msg=class Port") // delete when Port becomes private
 private[chisel3] case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition
 private[chisel3] case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command
 private[chisel3] case class WhenEnd(sourceInfo: SourceInfo, firrtlDepth: Int, hasAlt: Boolean = false) extends Command
@@ -799,7 +801,9 @@ private[chisel3] case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2
 private[chisel3] case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command
 private[chisel3] case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
 private[chisel3] case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition
-private[chisel3] case class Port(id: Data, dir: SpecifiedDirection)
+// Note this is just deprecated which will cause deprecation warnings, use @nowarn
+@deprecated("This API should never have been public, for Module port reflection, use DataMirror.modulePorts", "Chisel 3.5")
+case class Port(id: Data, dir: SpecifiedDirection)
 private[chisel3] case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition
 private[chisel3] object Formal extends Enumeration {
   val Assert = Value("assert")
@@ -808,12 +812,15 @@ private[chisel3] object Formal extends Enumeration {
 }
 private[chisel3] case class Verification[T <: VerificationStatement](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg,
                         predicate: Arg, message: String) extends Definition
+@nowarn("msg=class Port") // delete when Port becomes private
 private[chisel3] abstract class Component extends Arg {
   def id: BaseModule
   def name: String
   def ports: Seq[Port]
 }
+@nowarn("msg=class Port") // delete when Port becomes private
 private[chisel3] case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
+@nowarn("msg=class Port") // delete when Port becomes private
 private[chisel3] case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component
 
 case class Circuit(name: String, components: Seq[Component], annotations: Seq[ChiselAnnotation], renames: RenameMap) {
-- 
cgit v1.2.3


From f50f74f583fba7b98e550c440df091e559ce32b8 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Fri, 17 Dec 2021 17:17:03 -0800
Subject: Revert "Make stuff in IR.scala package private (#2274)" (#2308)

This reverts commit 21e324727e99f0bc124aaddea7fe294b4111c23a.

Note that I am keeping the change making Arg sealed.---
 .../main/scala/chisel3/internal/firrtl/IR.scala    | 84 +++++++++++-----------
 1 file changed, 42 insertions(+), 42 deletions(-)

(limited to 'core/src/main/scala/chisel3/internal')

diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index e3ea42c3..68f5f18e 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -16,11 +16,11 @@ import scala.math.BigDecimal.RoundingMode
 import scala.annotation.nowarn
 
 
-private[chisel3] case class PrimOp(name: String) {
+case class PrimOp(name: String) {
   override def toString: String = name
 }
 
-private[chisel3] object PrimOp {
+object PrimOp {
   val AddOp = PrimOp("add")
   val SubOp = PrimOp("sub")
   val TailOp = PrimOp("tail")
@@ -65,14 +65,14 @@ private[chisel3] object PrimOp {
   val AsAsyncResetOp = PrimOp("asAsyncReset")
 }
 
-sealed private[chisel3] abstract class Arg {
+sealed abstract class Arg {
   def localName: String = name
   def contextualName(ctx: Component): String = name
   def fullName(ctx: Component): String = contextualName(ctx)
   def name: String
 }
 
-private[chisel3] case class Node(id: HasId) extends Arg {
+case class Node(id: HasId) extends Arg {
   override def contextualName(ctx: Component): String = id.getOptionRef match {
     case Some(arg) => arg.contextualName(ctx)
     case None => id.instanceName
@@ -87,7 +87,7 @@ private[chisel3] case class Node(id: HasId) extends Arg {
   }
 }
 
-private[chisel3] object Arg {
+object Arg {
   def earlyLocalName(id: HasId): String = id.getOptionRef match {
     case Some(Index(Node(imm), Node(value))) => s"${earlyLocalName(imm)}[${earlyLocalName(imm)}]"
     case Some(Index(Node(imm), arg)) => s"${earlyLocalName(imm)}[${arg.localName}]"
@@ -100,7 +100,7 @@ private[chisel3] object Arg {
   }
 }
 
-private[chisel3] abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
+abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
   private[chisel3] def forcedWidth = widthArg.known
   private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
   override def contextualName(ctx: Component): String = name
@@ -126,11 +126,11 @@ private[chisel3] abstract class LitArg(val num: BigInt, widthArg: Width) extends
   }
 }
 
-private[chisel3] case class ILit(n: BigInt) extends Arg {
+case class ILit(n: BigInt) extends Arg {
   def name: String = n.toString
 }
 
-private[chisel3] case class ULit(n: BigInt, w: Width) extends LitArg(n, w) {
+case class ULit(n: BigInt, w: Width) extends LitArg(n, w) {
   def name: String = "UInt" + width + "(\"h0" + num.toString(16) + "\")"
   def minWidth: Int = 1 max n.bitLength
 
@@ -141,7 +141,7 @@ private[chisel3] case class ULit(n: BigInt, w: Width) extends LitArg(n, w) {
   require(n >= 0, s"UInt literal ${n} is negative")
 }
 
-private[chisel3] case class SLit(n: BigInt, w: Width) extends LitArg(n, w) {
+case class SLit(n: BigInt, w: Width) extends LitArg(n, w) {
   def name: String = {
     val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n
     s"asSInt(${ULit(unsigned, width).name})"
@@ -153,7 +153,7 @@ private[chisel3] case class SLit(n: BigInt, w: Width) extends LitArg(n, w) {
   }
 }
 
-private[chisel3] case class FPLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) {
+case class FPLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) {
   def name: String = {
     val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n
     s"asFixedPoint(${ULit(unsigned, width).name}, ${binaryPoint.asInstanceOf[KnownBinaryPoint].value})"
@@ -165,7 +165,7 @@ private[chisel3] case class FPLit(n: BigInt, w: Width, binaryPoint: BinaryPoint)
   }
 }
 
-private[chisel3] case class IntervalLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) {
+case class IntervalLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) {
   def name: String = {
     val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n
     s"asInterval(${ULit(unsigned, width).name}, ${n}, ${n}, ${binaryPoint.asInstanceOf[KnownBinaryPoint].value})"
@@ -181,12 +181,12 @@ private[chisel3] case class IntervalLit(n: BigInt, w: Width, binaryPoint: Binary
   }
 }
 
-private[chisel3] case class Ref(name: String) extends Arg
+case class Ref(name: String) extends Arg
 /** Arg for ports of Modules
   * @param mod the module this port belongs to
   * @param name the name of the port
   */
-private[chisel3] case class ModuleIO(mod: BaseModule, name: String) extends Arg {
+case class ModuleIO(mod: BaseModule, name: String) extends Arg {
   override def contextualName(ctx: Component): String =
     if (mod eq ctx.id) name else s"${mod.getRef.name}.$name"
 }
@@ -194,13 +194,13 @@ private[chisel3] case class ModuleIO(mod: BaseModule, name: String) extends Arg
   * @param mod The original module for which these ports are a clone
   * @param name the name of the module instance
   */
-private[chisel3] case class ModuleCloneIO(mod: BaseModule, name: String) extends Arg {
+case class ModuleCloneIO(mod: BaseModule, name: String) extends Arg {
   override def localName = ""
   override def contextualName(ctx: Component): String =
     // NOTE: mod eq ctx.id only occurs in Target and Named-related APIs
     if (mod eq ctx.id) localName else name
 }
-private[chisel3] case class Slot(imm: Node, name: String) extends Arg {
+case class Slot(imm: Node, name: String) extends Arg {
   override def contextualName(ctx: Component): String = {
     val immName = imm.contextualName(ctx)
     if (immName.isEmpty) name else s"$immName.$name"
@@ -211,7 +211,7 @@ private[chisel3] case class Slot(imm: Node, name: String) extends Arg {
   }
 }
 
-private[chisel3] case class Index(imm: Arg, value: Arg) extends Arg {
+case class Index(imm: Arg, value: Arg) extends Arg {
   def name: String = s"[$value]"
   override def contextualName(ctx: Component): String = s"${imm.contextualName(ctx)}[${value.contextualName(ctx)}]"
   override def localName: String = s"${imm.localName}[${value.localName}]"
@@ -775,53 +775,53 @@ sealed class IntervalRange(
   }
 }
 
-private[chisel3] abstract class Command {
+abstract class Command {
   def sourceInfo: SourceInfo
 }
-private[chisel3] abstract class Definition extends Command {
+abstract class Definition extends Command {
   def id: HasId
   def name: String = id.getRef.name
 }
-private[chisel3] case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition
-private[chisel3] case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command
-private[chisel3] case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition
-private[chisel3] case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition
-private[chisel3] case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
-private[chisel3] case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition
-private[chisel3] case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition
-private[chisel3] case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition
+case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition
+case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command
+case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition
+case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition
+case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
+case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition
+case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition
+case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition
 @nowarn("msg=class Port") // delete when Port becomes private
-private[chisel3] case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition
-private[chisel3] case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command
-private[chisel3] case class WhenEnd(sourceInfo: SourceInfo, firrtlDepth: Int, hasAlt: Boolean = false) extends Command
-private[chisel3] case class AltBegin(sourceInfo: SourceInfo) extends Command
-private[chisel3] case class OtherwiseEnd(sourceInfo: SourceInfo, firrtlDepth: Int) extends Command
-private[chisel3] case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
-private[chisel3] case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command
-private[chisel3] case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command
-private[chisel3] case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
-private[chisel3] case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition
+case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition
+case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command
+case class WhenEnd(sourceInfo: SourceInfo, firrtlDepth: Int, hasAlt: Boolean = false) extends Command
+case class AltBegin(sourceInfo: SourceInfo) extends Command
+case class OtherwiseEnd(sourceInfo: SourceInfo, firrtlDepth: Int) extends Command
+case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
+case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command
+case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command
+case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
+case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition
 // Note this is just deprecated which will cause deprecation warnings, use @nowarn
 @deprecated("This API should never have been public, for Module port reflection, use DataMirror.modulePorts", "Chisel 3.5")
 case class Port(id: Data, dir: SpecifiedDirection)
-private[chisel3] case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition
-private[chisel3] object Formal extends Enumeration {
+case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition
+object Formal extends Enumeration {
   val Assert = Value("assert")
   val Assume = Value("assume")
   val Cover = Value("cover")
 }
-private[chisel3] case class Verification[T <: VerificationStatement](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg,
+case class Verification[T <: VerificationStatement](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg,
                         predicate: Arg, message: String) extends Definition
 @nowarn("msg=class Port") // delete when Port becomes private
-private[chisel3] abstract class Component extends Arg {
+abstract class Component extends Arg {
   def id: BaseModule
   def name: String
   def ports: Seq[Port]
 }
 @nowarn("msg=class Port") // delete when Port becomes private
-private[chisel3] case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
+case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
 @nowarn("msg=class Port") // delete when Port becomes private
-private[chisel3] case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component
+case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component
 
 case class Circuit(name: String, components: Seq[Component], annotations: Seq[ChiselAnnotation], renames: RenameMap) {
   def firrtlAnnotations: Iterable[Annotation] = annotations.flatMap(_.toFirrtl.update(renames))
-- 
cgit v1.2.3