From d1d38bd096fce8b92468720fbedc835ecda40e6b Mon Sep 17 00:00:00 2001 From: Kevin Laeufer Date: Thu, 23 Sep 2021 11:12:26 -0700 Subject: make all verification statements publically available (#2089) --- core/src/main/scala/chisel3/internal/firrtl/Converter.scala | 4 ++-- core/src/main/scala/chisel3/internal/firrtl/IR.scala | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'core/src/main/scala/chisel3/internal/firrtl') diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala index f56c3b15..1dc52823 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -142,8 +142,8 @@ private[chisel3] object Converter { Some(fir.IsInvalid(convert(info), convert(arg, ctx, info))) case e @ DefInstance(info, id, _) => Some(fir.DefInstance(convert(info), e.name, id.name)) - case Stop(info, clock, ret) => - Some(fir.Stop(convert(info), ret, convert(clock, ctx, info), firrtl.Utils.one)) + case e @ Stop(_, info, clock, ret) => + Some(fir.Stop(convert(info), ret, convert(clock, ctx, info), firrtl.Utils.one, e.name)) case e @ Printf(_, info, clock, pable) => val (fmt, args) = unpack(pable, ctx) Some(fir.Print(convert(info), fir.StringLit(fmt), diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index 0b568548..1a06cd36 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -784,7 +784,7 @@ case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command -case class Stop(sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Command +case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition case class Port(id: Data, dir: SpecifiedDirection) case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition object Formal extends Enumeration { @@ -792,7 +792,7 @@ object Formal extends Enumeration { val Assume = Value("assume") val Cover = Value("cover") } -case class Verification[T <: BaseSim](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg, +case class Verification[T <: VerificationStatement](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg, predicate: Arg, message: String) extends Definition abstract class Component extends Arg { def id: BaseModule -- cgit v1.2.3 From 9dfee489b15642745174d191181ebf6f570db3ca Mon Sep 17 00:00:00 2001 From: Aditya Naik Date: Wed, 1 Dec 2021 16:09:34 -0800 Subject: Refactor Data.toString (#2197) Provides a more intuitive implementation of toString for Data. Utilizes the fact that the compiler plugin provides names earlier than Chisel had in the past so we can accurately guess the name of signals even in the currently elaborating module. Co-authored-by: Megan Wachs Co-authored-by: Jack Koenig --- core/src/main/scala/chisel3/internal/firrtl/IR.scala | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'core/src/main/scala/chisel3/internal/firrtl') diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index 1a06cd36..a352c96a 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -86,6 +86,19 @@ case class Node(id: HasId) extends Arg { } } +private[chisel3] object Arg { + def earlyLocalName(id: HasId): String = id.getOptionRef match { + case Some(Index(Node(imm), Node(value))) => s"${earlyLocalName(imm)}[${earlyLocalName(imm)}]" + case Some(Index(Node(imm), arg)) => s"${earlyLocalName(imm)}[${arg.localName}]" + case Some(Slot(Node(imm), name)) => s"${earlyLocalName(imm)}.$name" + case Some(arg) => arg.name + case None => id match { + case data: Data => data._computeName(None, Some("?")).get + case _ => "?" + } + } +} + abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { private[chisel3] def forcedWidth = widthArg.known private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth) @@ -196,7 +209,7 @@ case class Slot(imm: Node, name: String) extends Arg { if (immName.isEmpty) name else s"$immName.$name" } } -case class Index(imm: Arg, value: Arg) extends Arg { +case class Index(imm: Node, value: Arg) extends Arg { def name: String = s"[$value]" override def contextualName(ctx: Component): String = s"${imm.contextualName(ctx)}[${value.contextualName(ctx)}]" override def localName: String = s"${imm.localName}[${value.localName}]" -- cgit v1.2.3 From 21e324727e99f0bc124aaddea7fe294b4111c23a Mon Sep 17 00:00:00 2001 From: Aditya Naik Date: Tue, 14 Dec 2021 09:41:47 -0800 Subject: Make stuff in IR.scala package private (#2274) --- .../main/scala/chisel3/internal/firrtl/IR.scala | 85 +++++++++++----------- 1 file changed, 43 insertions(+), 42 deletions(-) (limited to 'core/src/main/scala/chisel3/internal/firrtl') diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index a352c96a..3279e9b9 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -15,11 +15,11 @@ import scala.collection.immutable.NumericRange import scala.math.BigDecimal.RoundingMode -case class PrimOp(name: String) { +private[chisel3] case class PrimOp(name: String) { override def toString: String = name } -object PrimOp { +private[chisel3] object PrimOp { val AddOp = PrimOp("add") val SubOp = PrimOp("sub") val TailOp = PrimOp("tail") @@ -64,14 +64,14 @@ object PrimOp { val AsAsyncResetOp = PrimOp("asAsyncReset") } -abstract class Arg { +sealed private[chisel3] abstract class Arg { def localName: String = name def contextualName(ctx: Component): String = name def fullName(ctx: Component): String = contextualName(ctx) def name: String } -case class Node(id: HasId) extends Arg { +private[chisel3] case class Node(id: HasId) extends Arg { override def contextualName(ctx: Component): String = id.getOptionRef match { case Some(arg) => arg.contextualName(ctx) case None => id.instanceName @@ -99,7 +99,7 @@ private[chisel3] object Arg { } } -abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { +private[chisel3] abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { private[chisel3] def forcedWidth = widthArg.known private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth) override def contextualName(ctx: Component): String = name @@ -125,11 +125,11 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { } } -case class ILit(n: BigInt) extends Arg { +private[chisel3] case class ILit(n: BigInt) extends Arg { def name: String = n.toString } -case class ULit(n: BigInt, w: Width) extends LitArg(n, w) { +private[chisel3] case class ULit(n: BigInt, w: Width) extends LitArg(n, w) { def name: String = "UInt" + width + "(\"h0" + num.toString(16) + "\")" def minWidth: Int = 1 max n.bitLength @@ -140,7 +140,7 @@ case class ULit(n: BigInt, w: Width) extends LitArg(n, w) { require(n >= 0, s"UInt literal ${n} is negative") } -case class SLit(n: BigInt, w: Width) extends LitArg(n, w) { +private[chisel3] case class SLit(n: BigInt, w: Width) extends LitArg(n, w) { def name: String = { val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n s"asSInt(${ULit(unsigned, width).name})" @@ -152,7 +152,7 @@ case class SLit(n: BigInt, w: Width) extends LitArg(n, w) { } } -case class FPLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) { +private[chisel3] case class FPLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) { def name: String = { val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n s"asFixedPoint(${ULit(unsigned, width).name}, ${binaryPoint.asInstanceOf[KnownBinaryPoint].value})" @@ -164,7 +164,7 @@ case class FPLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n } } -case class IntervalLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) { +private[chisel3] case class IntervalLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) { def name: String = { val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n s"asInterval(${ULit(unsigned, width).name}, ${n}, ${n}, ${binaryPoint.asInstanceOf[KnownBinaryPoint].value})" @@ -180,12 +180,12 @@ case class IntervalLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends Li } } -case class Ref(name: String) extends Arg +private[chisel3] case class Ref(name: String) extends Arg /** Arg for ports of Modules * @param mod the module this port belongs to * @param name the name of the port */ -case class ModuleIO(mod: BaseModule, name: String) extends Arg { +private[chisel3] case class ModuleIO(mod: BaseModule, name: String) extends Arg { override def contextualName(ctx: Component): String = if (mod eq ctx.id) name else s"${mod.getRef.name}.$name" } @@ -193,13 +193,13 @@ case class ModuleIO(mod: BaseModule, name: String) extends Arg { * @param mod The original module for which these ports are a clone * @param name the name of the module instance */ -case class ModuleCloneIO(mod: BaseModule, name: String) extends Arg { +private[chisel3] case class ModuleCloneIO(mod: BaseModule, name: String) extends Arg { override def localName = "" override def contextualName(ctx: Component): String = // NOTE: mod eq ctx.id only occurs in Target and Named-related APIs if (mod eq ctx.id) localName else name } -case class Slot(imm: Node, name: String) extends Arg { +private[chisel3] case class Slot(imm: Node, name: String) extends Arg { override def contextualName(ctx: Component): String = { val immName = imm.contextualName(ctx) if (immName.isEmpty) name else s"$immName.$name" @@ -209,7 +209,8 @@ case class Slot(imm: Node, name: String) extends Arg { if (immName.isEmpty) name else s"$immName.$name" } } -case class Index(imm: Node, value: Arg) extends Arg { + +private[chisel3] case class Index(imm: Arg, value: Arg) extends Arg { def name: String = s"[$value]" override def contextualName(ctx: Component): String = s"${imm.contextualName(ctx)}[${value.contextualName(ctx)}]" override def localName: String = s"${imm.localName}[${value.localName}]" @@ -773,47 +774,47 @@ sealed class IntervalRange( } } -abstract class Command { +private[chisel3] abstract class Command { def sourceInfo: SourceInfo } -abstract class Definition extends Command { +private[chisel3] abstract class Definition extends Command { def id: HasId def name: String = id.getRef.name } -case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition -case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command -case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition -case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition -case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition -case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition -case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition -case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition -case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition -case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command -case class WhenEnd(sourceInfo: SourceInfo, firrtlDepth: Int, hasAlt: Boolean = false) extends Command -case class AltBegin(sourceInfo: SourceInfo) extends Command -case class OtherwiseEnd(sourceInfo: SourceInfo, firrtlDepth: Int) extends Command -case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command -case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command -case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command -case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command -case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition -case class Port(id: Data, dir: SpecifiedDirection) -case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition -object Formal extends Enumeration { +private[chisel3] case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition +private[chisel3] case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command +private[chisel3] case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition +private[chisel3] case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition +private[chisel3] case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition +private[chisel3] case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition +private[chisel3] case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition +private[chisel3] case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition +private[chisel3] case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition +private[chisel3] case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command +private[chisel3] case class WhenEnd(sourceInfo: SourceInfo, firrtlDepth: Int, hasAlt: Boolean = false) extends Command +private[chisel3] case class AltBegin(sourceInfo: SourceInfo) extends Command +private[chisel3] case class OtherwiseEnd(sourceInfo: SourceInfo, firrtlDepth: Int) extends Command +private[chisel3] case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command +private[chisel3] case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command +private[chisel3] case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command +private[chisel3] case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command +private[chisel3] case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition +private[chisel3] case class Port(id: Data, dir: SpecifiedDirection) +private[chisel3] case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition +private[chisel3] object Formal extends Enumeration { val Assert = Value("assert") val Assume = Value("assume") val Cover = Value("cover") } -case class Verification[T <: VerificationStatement](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg, +private[chisel3] case class Verification[T <: VerificationStatement](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg, predicate: Arg, message: String) extends Definition -abstract class Component extends Arg { +private[chisel3] abstract class Component extends Arg { def id: BaseModule def name: String def ports: Seq[Port] } -case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component -case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component +private[chisel3] case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component +private[chisel3] case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component case class Circuit(name: String, components: Seq[Component], annotations: Seq[ChiselAnnotation], renames: RenameMap) { def firrtlAnnotations: Iterable[Annotation] = annotations.flatMap(_.toFirrtl.update(renames)) -- cgit v1.2.3 From 4ff431bb5c7978c9915bcd6080a4f27ef12ae607 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Wed, 15 Dec 2021 13:02:12 -0800 Subject: Restore Port to public API and deprecate (#2302) Also clean up deprecation warnings for replacement APIs and add clarifying ScalaDoc.--- core/src/main/scala/chisel3/internal/firrtl/Converter.scala | 3 ++- core/src/main/scala/chisel3/internal/firrtl/IR.scala | 9 ++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'core/src/main/scala/chisel3/internal/firrtl') diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala index 1dc52823..ac784882 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -7,10 +7,11 @@ import chisel3.internal.sourceinfo.{NoSourceInfo, SourceInfo, SourceLine, Unloca import firrtl.{ir => fir} import chisel3.internal.{HasId, castToInt, throwException} -import scala.annotation.tailrec +import scala.annotation.{nowarn, tailrec} import scala.collection.immutable.Queue import scala.collection.immutable.LazyList // Needed for 2.12 alias +@nowarn("msg=class Port") // delete when Port becomes private private[chisel3] object Converter { // TODO modeled on unpack method on Printable, refactor? def unpack(pable: Printable, ctx: Component): (String, Seq[Arg]) = pable match { diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index 3279e9b9..e3ea42c3 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -13,6 +13,7 @@ import _root_.firrtl.annotations.Annotation import scala.collection.immutable.NumericRange import scala.math.BigDecimal.RoundingMode +import scala.annotation.nowarn private[chisel3] case class PrimOp(name: String) { @@ -789,6 +790,7 @@ private[chisel3] case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: private[chisel3] case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition private[chisel3] case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition private[chisel3] case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition +@nowarn("msg=class Port") // delete when Port becomes private private[chisel3] case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition private[chisel3] case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command private[chisel3] case class WhenEnd(sourceInfo: SourceInfo, firrtlDepth: Int, hasAlt: Boolean = false) extends Command @@ -799,7 +801,9 @@ private[chisel3] case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2 private[chisel3] case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command private[chisel3] case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command private[chisel3] case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition -private[chisel3] case class Port(id: Data, dir: SpecifiedDirection) +// Note this is just deprecated which will cause deprecation warnings, use @nowarn +@deprecated("This API should never have been public, for Module port reflection, use DataMirror.modulePorts", "Chisel 3.5") +case class Port(id: Data, dir: SpecifiedDirection) private[chisel3] case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition private[chisel3] object Formal extends Enumeration { val Assert = Value("assert") @@ -808,12 +812,15 @@ private[chisel3] object Formal extends Enumeration { } private[chisel3] case class Verification[T <: VerificationStatement](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg, predicate: Arg, message: String) extends Definition +@nowarn("msg=class Port") // delete when Port becomes private private[chisel3] abstract class Component extends Arg { def id: BaseModule def name: String def ports: Seq[Port] } +@nowarn("msg=class Port") // delete when Port becomes private private[chisel3] case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component +@nowarn("msg=class Port") // delete when Port becomes private private[chisel3] case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component case class Circuit(name: String, components: Seq[Component], annotations: Seq[ChiselAnnotation], renames: RenameMap) { -- cgit v1.2.3 From f50f74f583fba7b98e550c440df091e559ce32b8 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Fri, 17 Dec 2021 17:17:03 -0800 Subject: Revert "Make stuff in IR.scala package private (#2274)" (#2308) This reverts commit 21e324727e99f0bc124aaddea7fe294b4111c23a. Note that I am keeping the change making Arg sealed.--- .../main/scala/chisel3/internal/firrtl/IR.scala | 84 +++++++++++----------- 1 file changed, 42 insertions(+), 42 deletions(-) (limited to 'core/src/main/scala/chisel3/internal/firrtl') diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index e3ea42c3..68f5f18e 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -16,11 +16,11 @@ import scala.math.BigDecimal.RoundingMode import scala.annotation.nowarn -private[chisel3] case class PrimOp(name: String) { +case class PrimOp(name: String) { override def toString: String = name } -private[chisel3] object PrimOp { +object PrimOp { val AddOp = PrimOp("add") val SubOp = PrimOp("sub") val TailOp = PrimOp("tail") @@ -65,14 +65,14 @@ private[chisel3] object PrimOp { val AsAsyncResetOp = PrimOp("asAsyncReset") } -sealed private[chisel3] abstract class Arg { +sealed abstract class Arg { def localName: String = name def contextualName(ctx: Component): String = name def fullName(ctx: Component): String = contextualName(ctx) def name: String } -private[chisel3] case class Node(id: HasId) extends Arg { +case class Node(id: HasId) extends Arg { override def contextualName(ctx: Component): String = id.getOptionRef match { case Some(arg) => arg.contextualName(ctx) case None => id.instanceName @@ -87,7 +87,7 @@ private[chisel3] case class Node(id: HasId) extends Arg { } } -private[chisel3] object Arg { +object Arg { def earlyLocalName(id: HasId): String = id.getOptionRef match { case Some(Index(Node(imm), Node(value))) => s"${earlyLocalName(imm)}[${earlyLocalName(imm)}]" case Some(Index(Node(imm), arg)) => s"${earlyLocalName(imm)}[${arg.localName}]" @@ -100,7 +100,7 @@ private[chisel3] object Arg { } } -private[chisel3] abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { +abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { private[chisel3] def forcedWidth = widthArg.known private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth) override def contextualName(ctx: Component): String = name @@ -126,11 +126,11 @@ private[chisel3] abstract class LitArg(val num: BigInt, widthArg: Width) extends } } -private[chisel3] case class ILit(n: BigInt) extends Arg { +case class ILit(n: BigInt) extends Arg { def name: String = n.toString } -private[chisel3] case class ULit(n: BigInt, w: Width) extends LitArg(n, w) { +case class ULit(n: BigInt, w: Width) extends LitArg(n, w) { def name: String = "UInt" + width + "(\"h0" + num.toString(16) + "\")" def minWidth: Int = 1 max n.bitLength @@ -141,7 +141,7 @@ private[chisel3] case class ULit(n: BigInt, w: Width) extends LitArg(n, w) { require(n >= 0, s"UInt literal ${n} is negative") } -private[chisel3] case class SLit(n: BigInt, w: Width) extends LitArg(n, w) { +case class SLit(n: BigInt, w: Width) extends LitArg(n, w) { def name: String = { val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n s"asSInt(${ULit(unsigned, width).name})" @@ -153,7 +153,7 @@ private[chisel3] case class SLit(n: BigInt, w: Width) extends LitArg(n, w) { } } -private[chisel3] case class FPLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) { +case class FPLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) { def name: String = { val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n s"asFixedPoint(${ULit(unsigned, width).name}, ${binaryPoint.asInstanceOf[KnownBinaryPoint].value})" @@ -165,7 +165,7 @@ private[chisel3] case class FPLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) } } -private[chisel3] case class IntervalLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) { +case class IntervalLit(n: BigInt, w: Width, binaryPoint: BinaryPoint) extends LitArg(n, w) { def name: String = { val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n s"asInterval(${ULit(unsigned, width).name}, ${n}, ${n}, ${binaryPoint.asInstanceOf[KnownBinaryPoint].value})" @@ -181,12 +181,12 @@ private[chisel3] case class IntervalLit(n: BigInt, w: Width, binaryPoint: Binary } } -private[chisel3] case class Ref(name: String) extends Arg +case class Ref(name: String) extends Arg /** Arg for ports of Modules * @param mod the module this port belongs to * @param name the name of the port */ -private[chisel3] case class ModuleIO(mod: BaseModule, name: String) extends Arg { +case class ModuleIO(mod: BaseModule, name: String) extends Arg { override def contextualName(ctx: Component): String = if (mod eq ctx.id) name else s"${mod.getRef.name}.$name" } @@ -194,13 +194,13 @@ private[chisel3] case class ModuleIO(mod: BaseModule, name: String) extends Arg * @param mod The original module for which these ports are a clone * @param name the name of the module instance */ -private[chisel3] case class ModuleCloneIO(mod: BaseModule, name: String) extends Arg { +case class ModuleCloneIO(mod: BaseModule, name: String) extends Arg { override def localName = "" override def contextualName(ctx: Component): String = // NOTE: mod eq ctx.id only occurs in Target and Named-related APIs if (mod eq ctx.id) localName else name } -private[chisel3] case class Slot(imm: Node, name: String) extends Arg { +case class Slot(imm: Node, name: String) extends Arg { override def contextualName(ctx: Component): String = { val immName = imm.contextualName(ctx) if (immName.isEmpty) name else s"$immName.$name" @@ -211,7 +211,7 @@ private[chisel3] case class Slot(imm: Node, name: String) extends Arg { } } -private[chisel3] case class Index(imm: Arg, value: Arg) extends Arg { +case class Index(imm: Arg, value: Arg) extends Arg { def name: String = s"[$value]" override def contextualName(ctx: Component): String = s"${imm.contextualName(ctx)}[${value.contextualName(ctx)}]" override def localName: String = s"${imm.localName}[${value.localName}]" @@ -775,53 +775,53 @@ sealed class IntervalRange( } } -private[chisel3] abstract class Command { +abstract class Command { def sourceInfo: SourceInfo } -private[chisel3] abstract class Definition extends Command { +abstract class Definition extends Command { def id: HasId def name: String = id.getRef.name } -private[chisel3] case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition -private[chisel3] case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command -private[chisel3] case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition -private[chisel3] case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition -private[chisel3] case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition -private[chisel3] case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition -private[chisel3] case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition -private[chisel3] case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition +case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition +case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command +case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition +case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition +case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition +case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition +case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition +case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition @nowarn("msg=class Port") // delete when Port becomes private -private[chisel3] case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition -private[chisel3] case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command -private[chisel3] case class WhenEnd(sourceInfo: SourceInfo, firrtlDepth: Int, hasAlt: Boolean = false) extends Command -private[chisel3] case class AltBegin(sourceInfo: SourceInfo) extends Command -private[chisel3] case class OtherwiseEnd(sourceInfo: SourceInfo, firrtlDepth: Int) extends Command -private[chisel3] case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command -private[chisel3] case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command -private[chisel3] case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command -private[chisel3] case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command -private[chisel3] case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition +case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition +case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command +case class WhenEnd(sourceInfo: SourceInfo, firrtlDepth: Int, hasAlt: Boolean = false) extends Command +case class AltBegin(sourceInfo: SourceInfo) extends Command +case class OtherwiseEnd(sourceInfo: SourceInfo, firrtlDepth: Int) extends Command +case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command +case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command +case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command +case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command +case class Stop(id: stop.Stop, sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Definition // Note this is just deprecated which will cause deprecation warnings, use @nowarn @deprecated("This API should never have been public, for Module port reflection, use DataMirror.modulePorts", "Chisel 3.5") case class Port(id: Data, dir: SpecifiedDirection) -private[chisel3] case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition -private[chisel3] object Formal extends Enumeration { +case class Printf(id: printf.Printf, sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Definition +object Formal extends Enumeration { val Assert = Value("assert") val Assume = Value("assume") val Cover = Value("cover") } -private[chisel3] case class Verification[T <: VerificationStatement](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg, +case class Verification[T <: VerificationStatement](id: T, op: Formal.Value, sourceInfo: SourceInfo, clock: Arg, predicate: Arg, message: String) extends Definition @nowarn("msg=class Port") // delete when Port becomes private -private[chisel3] abstract class Component extends Arg { +abstract class Component extends Arg { def id: BaseModule def name: String def ports: Seq[Port] } @nowarn("msg=class Port") // delete when Port becomes private -private[chisel3] case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component +case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component @nowarn("msg=class Port") // delete when Port becomes private -private[chisel3] case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component +case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component case class Circuit(name: String, components: Seq[Component], annotations: Seq[ChiselAnnotation], renames: RenameMap) { def firrtlAnnotations: Iterable[Annotation] = annotations.flatMap(_.toFirrtl.update(renames)) -- cgit v1.2.3