From f8053db3d20b733e0119b77595f0cdfcdab71057 Mon Sep 17 00:00:00 2001
From: Deborah Soung
Date: Thu, 24 Jun 2021 14:03:28 -0700
Subject: create and extend annotatable BaseSim class for verification nodes
 (#1968)

* prototype annotating verif constructs

* switch to final class

* name emissions

* moving BaseSim to experimental

* adding name tests

* fixing quotation escapes

* emitting names, but everything has a default name

* only name things with provided/suggested names

* name every BaseSim node

* removing msg, unused imports

* fixing file exist calls---
 .../main/scala/chisel3/experimental/package.scala  |  6 +++++
 .../experimental/verification/package.scala        | 28 +++++++++++++++++-----
 2 files changed, 28 insertions(+), 6 deletions(-)

(limited to 'core/src/main/scala/chisel3/experimental')

diff --git a/core/src/main/scala/chisel3/experimental/package.scala b/core/src/main/scala/chisel3/experimental/package.scala
index e8360430..8018159f 100644
--- a/core/src/main/scala/chisel3/experimental/package.scala
+++ b/core/src/main/scala/chisel3/experimental/package.scala
@@ -2,6 +2,7 @@
 
 package chisel3
 
+import chisel3.internal.NamedComponent
 import chisel3.internal.sourceinfo.SourceInfo
 
 /** Package for experimental features, which may have their API changed, be removed, etc.
@@ -165,4 +166,9 @@ package object experimental {
   val prefix = chisel3.internal.prefix
   // Use to remove prefixes not in provided scope
   val noPrefix = chisel3.internal.noPrefix
+
+  /** Base simulation-only component. */
+  abstract class BaseSim extends NamedComponent {
+    _parent.foreach(_.addId(this))
+  }
 }
diff --git a/core/src/main/scala/chisel3/experimental/verification/package.scala b/core/src/main/scala/chisel3/experimental/verification/package.scala
index 816299a3..ca15a5c4 100644
--- a/core/src/main/scala/chisel3/experimental/verification/package.scala
+++ b/core/src/main/scala/chisel3/experimental/verification/package.scala
@@ -8,36 +8,52 @@ import chisel3.internal.firrtl.{Formal, Verification}
 import chisel3.internal.sourceinfo.SourceInfo
 
 package object verification {
+
+  /** Named class for assertions. */
+  final class Assert(val predicate: Bool) extends BaseSim
+
+  /** Named class for assumes. */
+  final class Assume(val predicate: Bool) extends BaseSim
+
+  /** Named class for covers. */
+  final class Cover(val predicate: Bool) extends BaseSim
+
   object assert {
     def apply(predicate: Bool, msg: String = "")(
       implicit sourceInfo: SourceInfo,
-      compileOptions: CompileOptions): Unit = {
+      compileOptions: CompileOptions): Assert = {
+      val a = new Assert(predicate)
       when (!Module.reset.asBool) {
         val clock = Module.clock
-        Builder.pushCommand(Verification(Formal.Assert, sourceInfo, clock.ref, predicate.ref, msg))
+        Builder.pushCommand(Verification(a, Formal.Assert, sourceInfo, clock.ref, predicate.ref, msg))
       }
+      a
     }
   }
 
   object assume {
     def apply(predicate: Bool, msg: String = "")(
       implicit sourceInfo: SourceInfo,
-      compileOptions: CompileOptions): Unit = {
+      compileOptions: CompileOptions): Assume = {
+      val a = new Assume(predicate)
       when (!Module.reset.asBool) {
         val clock = Module.clock
-        Builder.pushCommand(Verification(Formal.Assume, sourceInfo, clock.ref, predicate.ref, msg))
+        Builder.pushCommand(Verification(a, Formal.Assume, sourceInfo, clock.ref, predicate.ref, msg))
       }
+      a
     }
   }
 
   object cover {
     def apply(predicate: Bool, msg: String = "")(
       implicit sourceInfo: SourceInfo,
-      compileOptions: CompileOptions): Unit = {
+      compileOptions: CompileOptions): Cover = {
       val clock = Module.clock
+      val c = new Cover(predicate)
       when (!Module.reset.asBool) {
-        Builder.pushCommand(Verification(Formal.Cover, sourceInfo, clock.ref, predicate.ref, msg))
+        Builder.pushCommand(Verification(c, Formal.Cover, sourceInfo, clock.ref, predicate.ref, msg))
       }
+      c
     }
   }
 }
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