From c4dec947d54a52c3092bd7855180d42afaae3776 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Sat, 13 Aug 2022 00:17:56 +0000 Subject: Add option to treat warnings as errors (backport #2676) (#2677) * Add option to treat warnings as errors (#2676) Add --warnings-as-errors option (cherry picked from commit 498946663726955c380a1e420f5d7b9630000aad) # Conflicts: # core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala # core/src/main/scala/chisel3/internal/Builder.scala # src/main/scala/chisel3/aop/injecting/InjectingAspect.scala # src/main/scala/chisel3/stage/ChiselOptions.scala # src/main/scala/chisel3/stage/package.scala # src/main/scala/chisel3/stage/phases/Elaborate.scala * Resolve backport conflicts Co-authored-by: Zachary Yedidia Co-authored-by: Jack Koenig --- core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'core/src/main/scala/chisel3/experimental') diff --git a/core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala b/core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala index 36bf6f87..99eacc7d 100644 --- a/core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala +++ b/core/src/main/scala/chisel3/experimental/hierarchy/Definition.scala @@ -103,7 +103,7 @@ object Definition extends SourceInfoDoc { ): Definition[T] = { val dynamicContext = { val context = Builder.captureContext() - new DynamicContext(Nil, context.throwOnFirstError, context.warnReflectiveNaming) + new DynamicContext(Nil, context.throwOnFirstError, context.warnReflectiveNaming, context.warningsAsErrors) } Builder.globalNamespace.copyTo(dynamicContext.globalNamespace) dynamicContext.inDefinition = true -- cgit v1.2.3 From 96830a4ad502019ff1040889a89375ff1e3a6c6b Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 16 Aug 2022 16:57:34 +0000 Subject: Add a cookbook and publicly visible scaladoc for prefix, noPrefix (#2687) (#2690) * Add a cookbook and publicly visible scaladoc for prefix, noPrefix (cherry picked from commit ae7dc30b3b99f1fbd91c35f54bc19be7c55f74a3) Co-authored-by: Megan Wachs --- .../main/scala/chisel3/experimental/package.scala | 28 ++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) (limited to 'core/src/main/scala/chisel3/experimental') diff --git a/core/src/main/scala/chisel3/experimental/package.scala b/core/src/main/scala/chisel3/experimental/package.scala index b1d9cae4..39131943 100644 --- a/core/src/main/scala/chisel3/experimental/package.scala +++ b/core/src/main/scala/chisel3/experimental/package.scala @@ -235,9 +235,33 @@ package object experimental { } } - // Use to add a prefix to any component generated in input scope + /** Use to add a prefix to any components generated in the provided scope. + * + * @example {{{ + * + * val x1 = prefix("first") { + * // Anything generated here will be prefixed with "first" + * } + * + * val x2 = prefix(mysignal) { + * // Anything generated here will be prefixed with the name of mysignal + * } + * + * }}} + */ val prefix = chisel3.internal.prefix - // Use to remove prefixes not in provided scope + + /** Use to clear existing prefixes so no signals within the scope are prefixed + * by signals/names outside the scope + * + * @example {{{ + * + * val x1 = prefix("first") { + * // Anything generated here will have no prefix. + * // The result returned from this would *still* be called `x1` however. + * } + * }}} + */ val noPrefix = chisel3.internal.noPrefix // ****************************** Hardware equivalents of Scala Tuples ****************************** -- cgit v1.2.3 From 5b13d04b28ddd05e4acbc5b9b3755c92ac0d9515 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Fri, 7 Oct 2022 19:56:19 +0000 Subject: Make nested IsInstantiables with Data in them work (#2761) (#2766) * Add unit test for Issue 2760 * checkpoint: Fix for nested instance * remove comments about stuff not working * make the test check the output a little more * relax the requirement on returning empty ioMap * Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala * Update core/src/main/scala/chisel3/Data.scala * Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala Co-authored-by: Jack Koenig * Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala Co-authored-by: Jack Koenig * Update core/src/main/scala/chisel3/experimental/hierarchy/core/Lookupable.scala * Add another unit test which unfortunately still passes * Update core/src/main/scala/chisel3/Data.scala * Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala Co-authored-by: Jack Koenig Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 1f9f26dc2bffcb4cc4daf2dc16c5cb455c6769ef) Co-authored-by: Megan Wachs --- .../chisel3/experimental/hierarchy/Lookupable.scala | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) (limited to 'core/src/main/scala/chisel3/experimental') diff --git a/core/src/main/scala/chisel3/experimental/hierarchy/Lookupable.scala b/core/src/main/scala/chisel3/experimental/hierarchy/Lookupable.scala index c83479b0..aa35455d 100644 --- a/core/src/main/scala/chisel3/experimental/hierarchy/Lookupable.scala +++ b/core/src/main/scala/chisel3/experimental/hierarchy/Lookupable.scala @@ -335,11 +335,20 @@ object Lookupable { } def instanceLookup[A](that: A => B, instance: Instance[A]): C = { val ret = that(instance.proto) - val ioMap: Option[Map[Data, Data]] = instance.underlying match { - case Clone(x: ModuleClone[_]) => Some(x.ioMap) - case Proto(x: BaseModule) => Some(x.getChiselPorts.map { case (_, data) => data -> data }.toMap) - case _ => None + + def getIoMap(hierarchy: Hierarchy[_]): Option[Map[Data, Data]] = { + hierarchy.underlying match { + case Clone(x: ModuleClone[_]) => Some(x.ioMap) + case Proto(x: BaseModule) => Some(x.getChiselPorts.map { case (_, data) => data -> data }.toMap) + case Clone(x: InstantiableClone[_]) => getIoMap(x._innerContext) + case Clone(x: InstanceClone[_]) => None + case other => { + Builder.exception(s"Internal Error! Unexpected case where we can't get IO Map: $other") + } + } } + val ioMap = getIoMap(instance) + if (isView(ret)) { cloneViewToContext(ret, instance.cache, ioMap, instance.getInnerDataContext) } else { -- cgit v1.2.3 From 721adc5c5509af48118afae44afa6b8a0107a926 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Mon, 10 Oct 2022 20:21:22 +0000 Subject: Fix traceName module type to RawModule (backport #2765) (#2768) * Fix traceName module type to RawModule (#2765) Change the type of modules that the traceName API can be used for from "Module" to "RawModule". This fixes a bug where this API couldn't be used for RawModules even though it totally works. Signed-off-by: Schuyler Eldridge Signed-off-by: Schuyler Eldridge (cherry picked from commit 74f1c85060cc72ebffe59a49f8d4539a464a4a19) * Fix binary compatibility issue Co-authored-by: Jack Koenig --- core/src/main/scala/chisel3/experimental/Trace.scala | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'core/src/main/scala/chisel3/experimental') diff --git a/core/src/main/scala/chisel3/experimental/Trace.scala b/core/src/main/scala/chisel3/experimental/Trace.scala index 4ab615a5..3cc27162 100644 --- a/core/src/main/scala/chisel3/experimental/Trace.scala +++ b/core/src/main/scala/chisel3/experimental/Trace.scala @@ -1,7 +1,7 @@ package chisel3.experimental import chisel3.internal.HasId -import chisel3.{Aggregate, Data, Element, Module} +import chisel3.{Aggregate, Data, Element, Module, RawModule} import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, CompleteTarget, SingleTargetAnnotation} import firrtl.transforms.DontTouchAllTargets @@ -22,7 +22,10 @@ import firrtl.transforms.DontTouchAllTargets object Trace { /** Trace a Instance name. */ - def traceName(x: Module): Unit = { + def traceName(x: Module): Unit = traceName(x: RawModule) + + /** Trace a Instance name. */ + def traceName(x: RawModule): Unit = { annotate(new ChiselAnnotation { def toFirrtl: Annotation = TraceNameAnnotation(x.toAbsoluteTarget, x.toAbsoluteTarget) }) -- cgit v1.2.3 From 9b8536b6af9f029a0edfb1c8df4f47a67e861c9d Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 18 Oct 2022 18:48:54 +0000 Subject: Add traceNameV2 for backwards compat. of traceName (#2784) (#2786) Add utilities to enable backwards compatibility of the Trace.traceName API to Chisel 3.5.x. This adds a Trace.traceNameV2 utility which aliases to Trace.traceName. This also removes the TraceNameAnnotation and renames it TraceAnnotation. In 3.5.x, traceName will point at TraceNameAnnotation (which has don't touch behavior) and will be deprecated telling people to use traceNameV2 which will point at TraceAnnotation (which does not have don't touch behavior). This will require fixups to the backport associated with this PR. Signed-off-by: Schuyler Eldridge (cherry picked from commit 47b7227e1ac7ccb0d48cefef03510542cc7e157e) # Conflicts: # core/src/main/scala/chisel3/experimental/Trace.scala Co-authored-by: Schuyler Eldridge --- .../main/scala/chisel3/experimental/Trace.scala | 43 +++++++++++++++++++++- 1 file changed, 41 insertions(+), 2 deletions(-) (limited to 'core/src/main/scala/chisel3/experimental') diff --git a/core/src/main/scala/chisel3/experimental/Trace.scala b/core/src/main/scala/chisel3/experimental/Trace.scala index 3cc27162..33d18147 100644 --- a/core/src/main/scala/chisel3/experimental/Trace.scala +++ b/core/src/main/scala/chisel3/experimental/Trace.scala @@ -22,16 +22,22 @@ import firrtl.transforms.DontTouchAllTargets object Trace { /** Trace a Instance name. */ + @deprecated("switch to traceNameV2 (until Chisel 3.6)", "3.5.5") def traceName(x: Module): Unit = traceName(x: RawModule) /** Trace a Instance name. */ + @deprecated("switch to traceNameV2 (until Chisel 3.6)", "3.5.5") def traceName(x: RawModule): Unit = { annotate(new ChiselAnnotation { def toFirrtl: Annotation = TraceNameAnnotation(x.toAbsoluteTarget, x.toAbsoluteTarget) }) } - /** Trace a Data name. */ + /** Trace a Data name. This adds "don't touch" semantics to anything traced. */ + @deprecated( + "switch to traceNameV2 (until Chisel 3.6) and add dontTouch if you want \"don't touch\" behavior", + "3.5.5" + ) def traceName(x: Data): Unit = { x match { case aggregate: Aggregate => @@ -46,7 +52,29 @@ object Trace { } } - /** An Annotation that records the original target annotate from Chisel. + /** Trace an Instance name. */ + def traceNameV2(x: RawModule): Unit = { + annotate(new ChiselAnnotation { + def toFirrtl: Annotation = TraceAnnotation(x.toAbsoluteTarget, x.toAbsoluteTarget) + }) + } + + /** Trace a Data name. This does NOT add "don't touch" semantics to the traced data. If you want this behavior, use an explicit [[chisel3.dontTouch]]. */ + def traceNameV2(x: Data): Unit = { + x match { + case aggregate: Aggregate => + annotate(new ChiselAnnotation { + def toFirrtl: Annotation = TraceAnnotation(aggregate.toAbsoluteTarget, aggregate.toAbsoluteTarget) + }) + aggregate.getElements.foreach(traceNameV2) + case element: Element => + annotate(new ChiselAnnotation { + def toFirrtl: Annotation = TraceAnnotation(element.toAbsoluteTarget, element.toAbsoluteTarget) + }) + } + } + + /** An Annotation that records the original target annotate from Chisel. This adds don't touch behavior. * * @param target target that should be renamed by [[firrtl.RenameMap]] in the firrtl transforms. * @param chiselTarget original annotated target in Chisel, which should not be changed or renamed in FIRRTL. @@ -57,6 +85,16 @@ object Trace { def duplicate(n: T): Annotation = this.copy(target = n) } + /** An Annotation that records the original target annotate from Chisel. This does NOT add don't touch behavior. + * + * @param target target that should be renamed by [[firrtl.RenameMap]] in the firrtl transforms. + * @param chiselTarget original annotated target in Chisel, which should not be changed or renamed in FIRRTL. + */ + private case class TraceAnnotation[T <: CompleteTarget](target: T, chiselTarget: T) + extends SingleTargetAnnotation[T] { + def duplicate(n: T): Annotation = this.copy(target = n) + } + /** Get [[CompleteTarget]] of the target `x` for `annos`. * This API can be used to find the final reference to a signal or module which is marked by `traceName` */ @@ -68,5 +106,6 @@ object Trace { */ def finalTargetMap(annos: AnnotationSeq): Map[CompleteTarget, Seq[CompleteTarget]] = annos.collect { case TraceNameAnnotation(t, chiselTarget) => chiselTarget -> t + case TraceAnnotation(t, chiselTarget) => chiselTarget -> t }.groupBy(_._1).map { case (k, v) => k -> v.map(_._2) } } -- cgit v1.2.3 From 4149157df6531d124483d992daf96cf4e62a0f0c Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Fri, 4 Nov 2022 18:20:07 +0000 Subject: Add PartialDataView.supertype (backport #2826) (#2827) * Add PartialDataView.supertype (#2826) This factory method makes it easy to create PartialDataViews from a Bundle type to its supertype. Because of the typing relationship, there is no need to provide a mapping between fields. The only thing necessary is to provide a function for constructing an instance of the supertype from an instance of the subtype. (cherry picked from commit 251d454a224e5a961438ba0ea41134d7da7a5992) # Conflicts: # core/src/main/scala/chisel3/experimental/dataview/package.scala # src/test/scala/chiselTests/experimental/DataView.scala * Resolve backport conflicts Co-authored-by: Jack Koenig --- .../chisel3/experimental/dataview/DataView.scala | 23 ++++++++++++++++++++++ .../chisel3/experimental/dataview/package.scala | 14 ++----------- 2 files changed, 25 insertions(+), 12 deletions(-) (limited to 'core/src/main/scala/chisel3/experimental') diff --git a/core/src/main/scala/chisel3/experimental/dataview/DataView.scala b/core/src/main/scala/chisel3/experimental/dataview/DataView.scala index 7f20964d..cc555b11 100644 --- a/core/src/main/scala/chisel3/experimental/dataview/DataView.scala +++ b/core/src/main/scala/chisel3/experimental/dataview/DataView.scala @@ -592,4 +592,27 @@ object PartialDataView { implicit sourceInfo: SourceInfo ): DataView[T, V] = new DataView[T, V](mkView, mapping, _total = false) + + /** Constructs a non-total [[DataView]] mapping from a [[Bundle]] type to a parent [[Bundle]] type + * + * @param mkView a function constructing an instance `V` from an instance of `T` + * @return the [[DataView]] that enables viewing instances of a [[Bundle]] as instances of a parent type + */ + def supertype[T <: Bundle, V <: Bundle]( + mkView: T => V + )( + implicit ev: SubTypeOf[T, V], + sourceInfo: SourceInfo + ): DataView[T, V] = + mapping[T, V]( + mkView, + { + case (a, b) => + val aElts = a.elements + val bElts = b.elements + val bKeys = bElts.keySet + val keys = aElts.keysIterator.filter(bKeys.contains) + keys.map(k => aElts(k) -> bElts(k)).toSeq + } + ) } diff --git a/core/src/main/scala/chisel3/experimental/dataview/package.scala b/core/src/main/scala/chisel3/experimental/dataview/package.scala index 71ae2d8f..a52e88cf 100644 --- a/core/src/main/scala/chisel3/experimental/dataview/package.scala +++ b/core/src/main/scala/chisel3/experimental/dataview/package.scala @@ -43,24 +43,14 @@ package object dataview { "${A} is not a subtype of ${B}! Did you mean .viewAs[${B}]? " + "Please see https://www.chisel-lang.org/chisel3/docs/cookbooks/dataview" ) - private type SubTypeOf[A, B] = A <:< B + private[dataview] type SubTypeOf[A, B] = A <:< B /** Provides `viewAsSupertype` for subclasses of [[Bundle]] */ implicit class BundleUpcastable[T <: Bundle](target: T) { /** View a [[Bundle]] or [[Record]] as a parent type (upcast) */ def viewAsSupertype[V <: Bundle](proto: V)(implicit ev: SubTypeOf[T, V], sourceInfo: SourceInfo): V = { - implicit val dataView = PartialDataView.mapping[T, V]( - _ => proto, - { - case (a, b) => - val aElts = a.elements - val bElts = b.elements - val bKeys = bElts.keySet - val keys = aElts.keysIterator.filter(bKeys.contains) - keys.map(k => aElts(k) -> bElts(k)).toSeq - } - ) + implicit val dataView = PartialDataView.supertype[T, V](_ => proto) target.viewAs[V] } } -- cgit v1.2.3 From 017bd6b9c96974df2a3c4f35e069d60fec001f2e Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Sat, 5 Nov 2022 22:31:07 +0000 Subject: Support Analog in DataView (#2782) (#2828) Co-authored-by: Megan Wachs (cherry picked from commit 26100a875c69bf56f7442fac82ca9c74ad3596eb) Co-authored-by: Jack Koenig --- .../main/scala/chisel3/experimental/Analog.scala | 3 +- .../main/scala/chisel3/experimental/Attach.scala | 45 ++++++++++++++++++++++ 2 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 core/src/main/scala/chisel3/experimental/Attach.scala (limited to 'core/src/main/scala/chisel3/experimental') diff --git a/core/src/main/scala/chisel3/experimental/Analog.scala b/core/src/main/scala/chisel3/experimental/Analog.scala index a366f0c3..7d89025c 100644 --- a/core/src/main/scala/chisel3/experimental/Analog.scala +++ b/core/src/main/scala/chisel3/experimental/Analog.scala @@ -69,7 +69,8 @@ final class Analog private (private[chisel3] val width: Width) extends Element { } targetTopBinding match { - case _: WireBinding | _: PortBinding => direction = ActualDirection.Bidirectional(ActualDirection.Default) + case _: WireBinding | _: PortBinding | _: ViewBinding | _: AggregateViewBinding => + direction = ActualDirection.Bidirectional(ActualDirection.Default) case x => throwException(s"Analog can only be Ports and Wires, not '$x'") } binding = target diff --git a/core/src/main/scala/chisel3/experimental/Attach.scala b/core/src/main/scala/chisel3/experimental/Attach.scala new file mode 100644 index 00000000..5c9cfe53 --- /dev/null +++ b/core/src/main/scala/chisel3/experimental/Attach.scala @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: Apache-2.0 + +package chisel3.experimental + +import chisel3.RawModule +import chisel3.internal._ +import chisel3.internal.Builder.pushCommand +import chisel3.internal.firrtl._ +import chisel3.internal.sourceinfo.SourceInfo + +object attach { + // Exceptions that can be generated by attach + case class AttachException(message: String) extends ChiselException(message) + def ConditionalAttachException: AttachException = + AttachException(": Conditional attach is not allowed!") + + // Actual implementation + private[chisel3] def impl(elts: Seq[Analog], contextModule: RawModule)(implicit sourceInfo: SourceInfo): Unit = { + if (Builder.whenDepth != 0) throw ConditionalAttachException + + // TODO Check that references are valid and can be attached + + pushCommand(Attach(sourceInfo, elts.map(_.lref))) + } + + /** Create an electrical connection between [[Analog]] components + * + * @param elts The components to attach + * + * @example + * {{{ + * val a1 = Wire(Analog(32.W)) + * val a2 = Wire(Analog(32.W)) + * attach(a1, a2) + * }}} + */ + def apply(elts: Analog*)(implicit sourceInfo: SourceInfo): Unit = { + try { + impl(elts, Builder.forcedUserModule) + } catch { + case AttachException(message) => + throwException(elts.mkString("Attaching (", ", ", s") failed @$message")) + } + } +} -- cgit v1.2.3 From f2ef3a8ee378a307661bd598cd44d4b895b9352e Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 8 Nov 2022 07:05:53 +0000 Subject: Improve Record.bind and Detect Records with unstable elements (backport #2829) (#2831) * Add Aggregate.elementsIterator and micro-optimize elementsIterator provides a more efficient API for iterating on the elements of Aggregates. It is especially useful for Records where getElements returns a Seq and thus eagerly constructs a new datastructure which may then just be iterated on anyway. This new elementsIterator API is then used throughout the codebase where it makes sense. Also change Vec.getElements to just return the underlying self instead of constructing a new Seq. (cherry picked from commit defa440b349031475daeff4024fad04925cccee6) # Conflicts: # core/src/main/scala/chisel3/Aggregate.scala # core/src/main/scala/chisel3/Module.scala # core/src/main/scala/chisel3/experimental/Trace.scala * Move Aggregate.bind inline into Record.bind Vec overrides bind and does not call the version in Aggregate so the version in Aggregate is misleading in that its only ever used by Records. Now there is no version in Aggregate and the actual functionality and use is more clear. (cherry picked from commit b054c30ba47026cb2a9b28c696a0a0a58b1e2ee7) # Conflicts: # core/src/main/scala/chisel3/Aggregate.scala * Extract and optimize duplicate checking Record.bind This replaces an immutable.Map with a single mutable.HashSet and saves the allocation of # elements Seqs. (cherry picked from commit 832ea52bc23424bb75b9654422b725a9cafaef40) # Conflicts: # core/src/main/scala/chisel3/Aggregate.scala * Add check for Records that define def elements (cherry picked from commit a4f223415de19e2a732e0b6a8fe681f706a19a56) * Resolve backport conflicts * Make elementsIterator final and package private * Waive false MiMa failure Co-authored-by: Jack Koenig --- core/src/main/scala/chisel3/experimental/Trace.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'core/src/main/scala/chisel3/experimental') diff --git a/core/src/main/scala/chisel3/experimental/Trace.scala b/core/src/main/scala/chisel3/experimental/Trace.scala index 33d18147..eb2ed46a 100644 --- a/core/src/main/scala/chisel3/experimental/Trace.scala +++ b/core/src/main/scala/chisel3/experimental/Trace.scala @@ -66,7 +66,7 @@ object Trace { annotate(new ChiselAnnotation { def toFirrtl: Annotation = TraceAnnotation(aggregate.toAbsoluteTarget, aggregate.toAbsoluteTarget) }) - aggregate.getElements.foreach(traceNameV2) + aggregate.elementsIterator.foreach(traceNameV2) case element: Element => annotate(new ChiselAnnotation { def toFirrtl: Annotation = TraceAnnotation(element.toAbsoluteTarget, element.toAbsoluteTarget) -- cgit v1.2.3 From bfa9f7465e6069b1e624126f9e14245b69e7c0a9 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Tue, 8 Nov 2022 17:27:07 +0000 Subject: Switch to using experimental trait for OpaqueTypes (backport #2783) (#2836) * Switch to using experimental trait for OpaqueTypes (#2783) This makes it more clear that the feature is experimental. Users may still override the opaqueType method for more dynamic control over when instances of a given Record are OpaqueTypes or not, but they are discouraged from doing so. (cherry picked from commit 7525dc71ccc2050d8e4a68b38f3b76920ba693fc) * Fix cloneType in RecordSpec Co-authored-by: Jack Koenig --- .../scala/chisel3/experimental/OpaqueType.scala | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 core/src/main/scala/chisel3/experimental/OpaqueType.scala (limited to 'core/src/main/scala/chisel3/experimental') diff --git a/core/src/main/scala/chisel3/experimental/OpaqueType.scala b/core/src/main/scala/chisel3/experimental/OpaqueType.scala new file mode 100644 index 00000000..e7a2a15d --- /dev/null +++ b/core/src/main/scala/chisel3/experimental/OpaqueType.scala @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: Apache-2.0 + +package chisel3.experimental + +import chisel3._ + +/** Indicates if this Record represents an "Opaque Type" + * + * Opaque types provide a mechanism for user-defined types + * that do not impose any "boxing" overhead in the emitted FIRRTL and Verilog. + * You can think about an opaque type Record as a box around + * a single element that only exists at Chisel elaboration time. + * Put another way, if this trait is mixed into a Record, + * the Record may only contain a single element with an empty name + * and there will be no `_` in the name for that element in the emitted Verilog. + * + * @see RecordSpec in Chisel's tests for example usage and expected output + */ +trait OpaqueType { self: Record => + + /** If set to true, indicates that this Record is an OpaqueType + * + * Users can override this if they need more dynamic control over the behavior for when + * instances of this type are considered opaque + */ + def opaqueType: Boolean = true +} -- cgit v1.2.3