From caf746088b7d92def18f2b3d6ccb7dfd9860e64b Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Fri, 31 May 2024 14:15:38 -0700
Subject: 52 errors, removing implicit sourceinfo to clear more errors

---
 core/src/main/scala/chisel3/UIntFactory.scala | 26 --------------------------
 1 file changed, 26 deletions(-)
 delete mode 100644 core/src/main/scala/chisel3/UIntFactory.scala

(limited to 'core/src/main/scala/chisel3/UIntFactory.scala')

diff --git a/core/src/main/scala/chisel3/UIntFactory.scala b/core/src/main/scala/chisel3/UIntFactory.scala
deleted file mode 100644
index 66c6f9c8..00000000
--- a/core/src/main/scala/chisel3/UIntFactory.scala
+++ /dev/null
@@ -1,26 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3
-
-import chisel3.internal.firrtl.{KnownWidth, ULit, UnknownWidth, Width}
-import firrtl.Utils
-import firrtl.constraint.IsKnown
-import firrtl.ir.{Closed, IntWidth, Open}
-
-// This is currently a factory because both Bits and UInt inherit it.
-trait UIntFactory {
-
-  /** Create a UInt type with inferred width. */
-  def apply(): UInt = apply(Width())
-
-  /** Create a UInt port with specified width. */
-  def apply(width: Width): UInt = new UInt(width)
-
-  /** Create a UInt literal with specified width. */
-  protected[chisel3] def Lit(value: BigInt, width: Width): UInt = {
-    val lit = ULit(value, width)
-    val result = new UInt(lit.width)
-    // Bind result to being an Literal
-    lit.bindLitArg(result)
-  }
-}
-- 
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