From d1d38bd096fce8b92468720fbedc835ecda40e6b Mon Sep 17 00:00:00 2001 From: Kevin Laeufer Date: Thu, 23 Sep 2021 11:12:26 -0700 Subject: make all verification statements publically available (#2089) --- core/src/main/scala/chisel3/RawModule.scala | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'core/src/main/scala/chisel3/RawModule.scala') diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index 27f16ad4..f1b4c1cf 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -5,7 +5,7 @@ package chisel3 import scala.collection.mutable.{ArrayBuffer, HashMap} import scala.util.Try import scala.language.experimental.macros -import chisel3.experimental.{BaseModule, BaseSim} +import chisel3.experimental.BaseModule import chisel3.internal._ import chisel3.internal.BaseModule.{ModuleClone, InstanceClone} import chisel3.internal.Builder._ @@ -81,7 +81,11 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) case id: InstanceClone[_] => id.setAsInstanceRef() case id: BaseModule => id.forceName(None, default=id.desiredName, _namespace) case id: MemBase[_] => id.forceName(None, default="MEM", _namespace) - case id: BaseSim => id.forceName(None, default="SIM", _namespace) + case id: stop.Stop => id.forceName(None, default="stop", _namespace) + case id: assert.Assert => id.forceName(None, default="assert", _namespace) + case id: assume.Assume => id.forceName(None, default="assume", _namespace) + case id: cover.Cover => id.forceName(None, default="cover", _namespace) + case id: printf.Printf => id.forceName(None, default="printf", _namespace) case id: Data => if (id.isSynthesizable) { id.topBinding match { -- cgit v1.2.3 From c2985aa6ef95a45d6ce9663a17f835eaba0cb9c5 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Tue, 5 Oct 2021 13:20:28 -0700 Subject: Fix naming of unwrapped val io in Chisel.Modules (#2150) The removal of virtual method io accidentally made the naming of io in compatibility mode Bundles sensitive to the prefix at the time of the first access of the field. It also made .suggestName able to override the name. This commit fixes that issue by forcing the name of the io Data to be "io" no matter what.--- core/src/main/scala/chisel3/RawModule.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'core/src/main/scala/chisel3/RawModule.scala') diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index f1b4c1cf..c001772b 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -199,7 +199,7 @@ package object internal { tryJavaReflect .orElse(tryScalaReflect) - .map(_.autoSeed("io")) + .map(_.forceFinalName("io")) .orElse { // Fallback if reflection fails, user can wrap in IO(...) self.findPort("io") -- cgit v1.2.3 From d6907893f019ee86573dc81768884150e541dba3 Mon Sep 17 00:00:00 2001 From: Aditya Naik Date: Wed, 20 Oct 2021 00:13:34 -0400 Subject: Update computeName and callsites (#2192) Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>--- core/src/main/scala/chisel3/RawModule.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'core/src/main/scala/chisel3/RawModule.scala') diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index c001772b..d8781ee0 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -44,7 +44,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) private[chisel3] def namePorts(names: HashMap[HasId, String]): Unit = { for (port <- getModulePorts) { - port.computeName(None, None).orElse(names.get(port)) match { + port._computeName(None, None).orElse(names.get(port)) match { case Some(name) => if (_namespace.contains(name)) { Builder.error(s"""Unable to name port $port to "$name" in $this,""" + -- cgit v1.2.3 From 4ff431bb5c7978c9915bcd6080a4f27ef12ae607 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Wed, 15 Dec 2021 13:02:12 -0800 Subject: Restore Port to public API and deprecate (#2302) Also clean up deprecation warnings for replacement APIs and add clarifying ScalaDoc.--- core/src/main/scala/chisel3/RawModule.scala | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'core/src/main/scala/chisel3/RawModule.scala') diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index d8781ee0..e977d918 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -5,6 +5,7 @@ package chisel3 import scala.collection.mutable.{ArrayBuffer, HashMap} import scala.util.Try import scala.language.experimental.macros +import scala.annotation.nowarn import chisel3.experimental.BaseModule import chisel3.internal._ import chisel3.internal.BaseModule.{ModuleClone, InstanceClone} @@ -17,6 +18,7 @@ import _root_.firrtl.annotations.{IsModule, ModuleTarget} * This abstract base class is a user-defined module which does not include implicit clock and reset and supports * multiple IO() declarations. */ +@nowarn("msg=class Port") // delete when Port becomes private abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends BaseModule { // @@ -35,10 +37,10 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) // // Other Internal Functions // - // For debuggers/testers, TODO: refactor out into proper public API private var _firrtlPorts: Option[Seq[firrtl.Port]] = None - @deprecated("Use DataMirror.fullModulePorts instead. this API will be removed in Chisel 3.6", "Chisel 3.5") - lazy val getPorts = _firrtlPorts.get + + @deprecated("Use DataMirror.modulePorts instead. this API will be removed in Chisel 3.6", "Chisel 3.5") + lazy val getPorts: Seq[Port] = _firrtlPorts.get val compileOptions = moduleCompileOptions -- cgit v1.2.3