From a529d0e962cbe6a8f32dcc87d5193df46c0ebc94 Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Mon, 3 Jun 2024 09:44:01 -0700
Subject: Get core to compile

---
 core/src/main/scala/chisel3/RawModule.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'core/src/main/scala/chisel3/RawModule.scala')

diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index 01e5f9f5..4e724b1b 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -114,7 +114,7 @@ abstract class RawModule extends BaseModule {
     _component
   }
 
-  private[chisel3] def initializeInParent: Unit = {}
+  private[chisel3] def initializeInParent(): Unit = {}
 }
 
 trait RequireAsyncReset extends Module {
-- 
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