From 5ecde24d390248722f8ab6ac790fbd1d453e898e Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Fri, 31 Jul 2020 11:05:13 -0700
Subject: Check whether signals escape their when scopes (#1518)

* Include and check when scoping as part of reg/mem/wire/node bindings

* Allow outdated 'when' behavior of CHIRRTL memory ports with enables

* Extend cross-module / when-visibility checks to all data refs

* Fixes #1512
* Cannot be checked if outside a module context
* E.g. delayed evaluation of printf / assert args

* Add basic test cases for cross-module refs / signals escaping when scopes

* Remove illegal cross-module references from existing tests---
 core/src/main/scala/chisel3/RawModule.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'core/src/main/scala/chisel3/RawModule.scala')

diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index 5b609384..a1006594 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -80,15 +80,15 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
         case id: Data  =>
           if (id.isSynthesizable) {
             id.topBinding match {
-              case OpBinding(_) =>
+              case OpBinding(_, _) =>
                 id.forceName(Some(""), default="T", _namespace)
-              case MemoryPortBinding(_) =>
+              case MemoryPortBinding(_, _) =>
                 id.forceName(None, default="MPORT", _namespace)
               case PortBinding(_) =>
                 id.forceName(None, default="PORT", _namespace)
-              case RegBinding(_) =>
+              case RegBinding(_, _) =>
                 id.forceName(None, default="REG", _namespace)
-              case WireBinding(_) =>
+              case WireBinding(_, _) =>
                 id.forceName(Some(""), default="WIRE", _namespace)
               case _ =>  // don't name literals
             }
-- 
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