From ef8a9c2148f01e058d2986c9d64f0c35f640790c Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Wed, 27 Oct 2021 16:52:56 -0700
Subject: Add Select APIs for Hierarchy package (#2210)

* Add Hierarchy trait

* Add Hierarchy trait

* Add Hierarchy scaladoc

* Add license

* Add isA and tests

* Add back isA

* Add new Select APIs for hierarchy package

* Update scaladoc

* Write outlines for tests

* Add tests and fixes to new Select functions

* Make calculate via lazy val

* Apply suggestions from code review

Co-authored-by: Megan Wachs <megan@sifive.com>

* Apply suggestions from code review

Co-authored-by: Megan Wachs <megan@sifive.com>

* Clean up scaladoc

* Add shouldNot compile

* Apply suggestions from code review

Co-authored-by: Megan Wachs <megan@sifive.com>

* Bugfix all funcs should analyze root too

* Add mdoc, bugfix toDefinition

* Make func private, add scaladoc

* Update src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Made protected vals private

* Apply suggestions from code review

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Address code review comments

* Added additional null check

Co-authored-by: Megan Wachs <megan@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>---
 core/src/main/scala/chisel3/Module.scala | 26 +++++++++++++++++++++-----
 1 file changed, 21 insertions(+), 5 deletions(-)

(limited to 'core/src/main/scala/chisel3/Module.scala')

diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index 1ae65969..263aee61 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -88,6 +88,16 @@ object Module extends SourceInfoDoc {
   def reset: Reset = Builder.forcedReset
   /** Returns the current Module */
   def currentModule: Option[BaseModule] = Builder.currentModule
+
+  private[chisel3] def do_pseudo_apply[T <: BaseModule](bc: => T)
+                               (implicit sourceInfo: SourceInfo,
+                                         compileOptions: CompileOptions): T = {
+    val parent = Builder.currentModule
+
+    val module: T = bc  // bc is actually evaluated here
+
+    module
+  }
 }
 
 /** Abstract base class for Modules, which behave much like Verilog modules.
@@ -357,13 +367,19 @@ package experimental {
     //
     // Builder Internals - this tracks which Module RTL construction belongs to.
     //
-    if (!Builder.readyForModuleConstr) {
-      throwException("Error: attempted to instantiate a Module without wrapping it in Module().")
+    this match {
+      case _: PseudoModule =>
+      case other =>
+        if (!Builder.readyForModuleConstr) {
+          throwException("Error: attempted to instantiate a Module without wrapping it in Module().")
+        }
     }
-    readyForModuleConstr = false
+    if (Builder.hasDynamicContext) {
+      readyForModuleConstr = false
 
-    Builder.currentModule = Some(this)
-    Builder.whenStack = Nil
+      Builder.currentModule = Some(this)
+      Builder.whenStack = Nil
+    }
 
     //
     // Module Construction Internals
-- 
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