From 5ece5aa8ac2716d66a6ed91e38a978049d8bf250 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Wed, 20 Jan 2021 13:46:48 -0800 Subject: Rename MultiIOModule to Module --- core/src/main/scala/chisel3/Module.scala | 44 +++++++++++++++++++++++++++++--- 1 file changed, 40 insertions(+), 4 deletions(-) (limited to 'core/src/main/scala/chisel3/Module.scala') diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala index 236f528e..27b38d0c 100644 --- a/core/src/main/scala/chisel3/Module.scala +++ b/core/src/main/scala/chisel3/Module.scala @@ -6,15 +6,14 @@ import scala.collection.immutable.ListMap import scala.collection.mutable.{ArrayBuffer, HashMap} import scala.collection.JavaConversions._ import scala.language.experimental.macros - import java.util.IdentityHashMap import chisel3.internal._ import chisel3.internal.Builder._ import chisel3.internal.firrtl._ -import chisel3.internal.sourceinfo.{InstTransform, SourceInfo} +import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo} import chisel3.experimental.BaseModule -import _root_.firrtl.annotations.{ModuleName, ModuleTarget, IsModule} +import _root_.firrtl.annotations.{IsModule, ModuleName, ModuleTarget} object Module extends SourceInfoDoc { /** A wrapper method that all Module instantiations must be wrapped in @@ -87,6 +86,43 @@ object Module extends SourceInfoDoc { def currentModule: Option[BaseModule] = Builder.currentModule } +/** Abstract base class for Modules, which behave much like Verilog modules. + * These may contain both logic and state which are written in the Module + * body (constructor). + * This abstract base class includes an implicit clock and reset. + * + * @note Module instantiations must be wrapped in a Module() call. + */ +abstract class Module(implicit moduleCompileOptions: CompileOptions) extends RawModule { + // Implicit clock and reset pins + final val clock: Clock = IO(Input(Clock())).suggestName("clock") + final val reset: Reset = IO(Input(mkReset)).suggestName("reset") + + // These are to be phased out + protected var override_clock: Option[Clock] = None + protected var override_reset: Option[Bool] = None + + private[chisel3] def mkReset: Reset = { + // Top module and compatibility mode use Bool for reset + val inferReset = _parent.isDefined && moduleCompileOptions.inferModuleReset + if (inferReset) Reset() else Bool() + } + + // Setup ClockAndReset + Builder.currentClock = Some(clock) + Builder.currentReset = Some(reset) + Builder.clearPrefix() + + private[chisel3] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = { + implicit val sourceInfo = UnlocatableSourceInfo + + super.initializeInParent(parentCompileOptions) + clock := override_clock.getOrElse(Builder.forcedClock) + reset := override_reset.getOrElse(Builder.forcedReset) + } +} + + package experimental { object IO { @@ -145,7 +181,7 @@ package internal { if (!compileOptions.explicitInvalidate) { pushCommand(DefInvalid(sourceInfo, clonePorts.ref)) } - if (proto.isInstanceOf[MultiIOModule]) { + if (proto.isInstanceOf[Module]) { clonePorts("clock") := Module.clock clonePorts("reset") := Module.reset } -- cgit v1.2.3 From b88ae1fb5cd106f114fa2152ac53c197ae69c164 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Wed, 20 Jan 2021 14:40:11 -0800 Subject: Deprecate override_clock and override_reset in Module --- core/src/main/scala/chisel3/Module.scala | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) (limited to 'core/src/main/scala/chisel3/Module.scala') diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala index 27b38d0c..9a1a0ce1 100644 --- a/core/src/main/scala/chisel3/Module.scala +++ b/core/src/main/scala/chisel3/Module.scala @@ -98,9 +98,22 @@ abstract class Module(implicit moduleCompileOptions: CompileOptions) extends Raw final val clock: Clock = IO(Input(Clock())).suggestName("clock") final val reset: Reset = IO(Input(mkReset)).suggestName("reset") - // These are to be phased out - protected var override_clock: Option[Clock] = None - protected var override_reset: Option[Bool] = None + // TODO It's hard to remove these deprecated override methods because they're used by + // Chisel.QueueCompatibility which extends chisel3.Queue which extends chisel3.Module + private var _override_clock: Option[Clock] = None + private var _override_reset: Option[Bool] = None + @deprecated("Use withClock at Module instantiation", "Chisel 3.5") + protected def override_clock: Option[Clock] = _override_clock + @deprecated("Use withClock at Module instantiation", "Chisel 3.5") + protected def override_reset: Option[Bool] = _override_reset + @deprecated("Use withClock at Module instantiation", "Chisel 3.5") + protected def override_clock_=(rhs: Option[Clock]): Unit = { + _override_clock = rhs + } + @deprecated("Use withClock at Module instantiation", "Chisel 3.5") + protected def override_reset_=(rhs: Option[Bool]): Unit = { + _override_reset = rhs + } private[chisel3] def mkReset: Reset = { // Top module and compatibility mode use Bool for reset @@ -117,8 +130,8 @@ abstract class Module(implicit moduleCompileOptions: CompileOptions) extends Raw implicit val sourceInfo = UnlocatableSourceInfo super.initializeInParent(parentCompileOptions) - clock := override_clock.getOrElse(Builder.forcedClock) - reset := override_reset.getOrElse(Builder.forcedReset) + clock := _override_clock.getOrElse(Builder.forcedClock) + reset := _override_reset.getOrElse(Builder.forcedReset) } } -- cgit v1.2.3 From 8a73362bb6fe87817a1867cc2482c1841f95c077 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Wed, 20 Jan 2021 18:55:16 -0800 Subject: Remove val io Chisel projects no longer need -Xsource:2.11 when compiling with Scala 2.12. Autowrapping of "val io" for compatibility mode Modules is now implemented using reflection instead of calling the virtual method. Also move Chisel.BlackBox to new chisel3.internal.LegacyBlackBox --- core/src/main/scala/chisel3/Module.scala | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'core/src/main/scala/chisel3/Module.scala') diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala index 9a1a0ce1..d34211f1 100644 --- a/core/src/main/scala/chisel3/Module.scala +++ b/core/src/main/scala/chisel3/Module.scala @@ -257,6 +257,11 @@ package experimental { // mainly for compatibility purposes. protected def portsContains(elem: Data): Boolean = _ports contains elem + // This is dangerous because it can be called before the module is closed and thus there could + // be more ports and names have not yet been finalized. + // This should only to be used during the process of closing when it is safe to do so. + private[chisel3] def findPort(name: String): Option[Data] = _ports.find(_.seedOpt.contains(name)) + protected def portsSize: Int = _ports.size /** Generates the FIRRTL Component (Module or Blackbox) of this Module. -- cgit v1.2.3