From be4463a7756351dcab09ba3f576f5e3687fb0ebf Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Thu, 10 Nov 2022 20:03:45 +0000 Subject: Unify Chisel2 and chisel3 directionality (backport #2634) (#2837) * Unify Chisel2 and chisel3 directionality (#2634) Co-authored-by: Jack Koenig (cherry picked from commit 1aea4ef96466cbe08150d20c85c88b81e4e4f80f) # Conflicts: # core/src/main/scala/chisel3/Aggregate.scala # core/src/main/scala/chisel3/Module.scala # src/test/scala/chiselTests/Direction.scala * fix up backport * fix up backport * clean up diff * make test order like it was on master Co-authored-by: Adam Izraelevitz Co-authored-by: Megan Wachs --- core/src/main/scala/chisel3/Module.scala | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) (limited to 'core/src/main/scala/chisel3/Module.scala') diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala index 9315a44b..48c33083 100644 --- a/core/src/main/scala/chisel3/Module.scala +++ b/core/src/main/scala/chisel3/Module.scala @@ -692,33 +692,34 @@ package experimental { */ protected def _bindIoInPlace(iodef: Data): Unit = { // Compatibility code: Chisel2 did not require explicit direction on nodes - // (unspecified treated as output, and flip on nothing was input). - // This sets assigns the explicit directions required by newer semantics on - // Bundles defined in compatibility mode. + // (unspecified treated as output, and flip on nothing was input). + // However, we are going to go back to Chisel2 semantics, so we need to make it work + // even for chisel3 code. + // This assigns the explicit directions required by both semantics on all Bundles. // This recursively walks the tree, and assigns directions if no explicit - // direction given by upper-levels (override Input / Output) AND element is - // directly inside a compatibility Bundle determined by compile options. - def assignCompatDir(data: Data, insideCompat: Boolean): Unit = { + // direction given by upper-levels (override Input / Output) + def assignCompatDir(data: Data): Unit = { data match { - case data: Element if insideCompat => data._assignCompatibilityExplicitDirection - case data: Element => // Not inside a compatibility Bundle, nothing to be done + case data: Element => data._assignCompatibilityExplicitDirection case data: Aggregate => data.specifiedDirection match { // Recurse into children to ensure explicit direction set somewhere case SpecifiedDirection.Unspecified | SpecifiedDirection.Flip => data match { case record: Record => - val compatRecord = !record.compileOptions.dontAssumeDirectionality - record.elementsIterator.foreach(assignCompatDir(_, compatRecord)) + record.elementsIterator.foreach(assignCompatDir(_)) case vec: Vec[_] => - vec.elementsIterator.foreach(assignCompatDir(_, insideCompat)) + vec.elementsIterator.foreach(assignCompatDir(_)) } - case SpecifiedDirection.Input | SpecifiedDirection.Output => // forced assign, nothing to do + case SpecifiedDirection.Input | SpecifiedDirection.Output => + // forced assign, nothing to do + // Note this is because Input and Output recurse down their types to align all fields to that SpecifiedDirection + // Thus, no implicit assigment is necessary. } } } - assignCompatDir(iodef, false) + assignCompatDir(iodef) iodef.bind(PortBinding(this)) _ports += iodef -- cgit v1.2.3