From 5ecde24d390248722f8ab6ac790fbd1d453e898e Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Fri, 31 Jul 2020 11:05:13 -0700
Subject: Check whether signals escape their when scopes (#1518)

* Include and check when scoping as part of reg/mem/wire/node bindings

* Allow outdated 'when' behavior of CHIRRTL memory ports with enables

* Extend cross-module / when-visibility checks to all data refs

* Fixes #1512
* Cannot be checked if outside a module context
* E.g. delayed evaluation of printf / assert args

* Add basic test cases for cross-module refs / signals escaping when scopes

* Remove illegal cross-module references from existing tests---
 core/src/main/scala/chisel3/Module.scala | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'core/src/main/scala/chisel3/Module.scala')

diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index 25037b00..194c546c 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -37,7 +37,7 @@ object Module extends SourceInfoDoc {
     Builder.readyForModuleConstr = true
 
     val parent = Builder.currentModule
-    val whenDepth: Int = Builder.whenDepth
+    val parentWhenStack = Builder.whenStack
 
     // Save then clear clock and reset to prevent leaking scope, must be set again in the Module
     val (saveClock, saveReset)  = (Builder.currentClock, Builder.currentReset)
@@ -49,7 +49,7 @@ object Module extends SourceInfoDoc {
     // Execute the module, this has the following side effects:
     //   - set currentModule
     //   - unset readyForModuleConstr
-    //   - reset whenDepth to 0
+    //   - reset whenStack to be empty
     //   - set currentClockAndReset
     val module: T = bc  // bc is actually evaluated here
 
@@ -62,7 +62,7 @@ object Module extends SourceInfoDoc {
                      sourceInfo.makeMessage(" See " + _))
     }
     Builder.currentModule = parent // Back to parent!
-    Builder.whenDepth = whenDepth
+    Builder.whenStack = parentWhenStack
     Builder.currentClock = saveClock   // Back to clock and reset scope
     Builder.currentReset = saveReset
 
@@ -137,7 +137,7 @@ package internal {
     private[chisel3] def cloneIORecord(proto: BaseModule)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): ClonePorts = {
       require(proto.isClosed, "Can't clone a module before module close")
       val clonePorts = new ClonePorts(proto.getModulePorts: _*)
-      clonePorts.bind(WireBinding(Builder.forcedUserModule))
+      clonePorts.bind(WireBinding(Builder.forcedUserModule, Builder.currentWhen()))
       val cloneInstance = new DefInstance(sourceInfo, proto, proto._component.get.ports) {
         override def name = clonePorts.getRef.name
       }
@@ -169,7 +169,7 @@ package experimental {
     readyForModuleConstr = false
 
     Builder.currentModule = Some(this)
-    Builder.whenDepth = 0
+    Builder.whenStack = Nil
 
     //
     // Module Construction Internals
-- 
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