From 3aed65709aedc22810926751db33fe9ba767a03b Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Fri, 27 May 2022 22:06:36 +0000 Subject: Make ExtModule port naming consistent with Module (#2548) (#2549) ExtModule now uses the same namePorts implementation as regular Modules. Previously, ExtModules only allowed port naming via runtime reflection. This meant that .suggestName and other naming APIs do not work. It also breaks FlatIO for ExtModule which is a potential replacement API for BlackBox's special `val io` handling. (cherry picked from commit 83cccfb782d9141bf2c843246c2a525c62392924) Co-authored-by: Jack Koenig --- core/src/main/scala/chisel3/Module.scala | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'core/src/main/scala/chisel3/Module.scala') diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala index 84139630..3382cd1b 100644 --- a/core/src/main/scala/chisel3/Module.scala +++ b/core/src/main/scala/chisel3/Module.scala @@ -486,6 +486,27 @@ package experimental { */ private[chisel3] def initializeInParent(parentCompileOptions: CompileOptions): Unit + private[chisel3] def namePorts(names: HashMap[HasId, String]): Unit = { + for (port <- getModulePorts) { + port._computeName(None, None).orElse(names.get(port)) match { + case Some(name) => + if (_namespace.contains(name)) { + Builder.error( + s"""Unable to name port $port to "$name" in $this,""" + + " name is already taken by another port!" + ) + } + port.setRef(ModuleIO(this, _namespace.name(name))) + case None => + Builder.error( + s"Unable to name port $port in $this, " + + "try making it a public field of the Module" + ) + port.setRef(ModuleIO(this, "")) + } + } + } + // // Chisel Internals // -- cgit v1.2.3 From a689c7c0dd336fe0b9db6171786993b190a700f8 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Wed, 8 Jun 2022 20:09:45 +0000 Subject: Added migration for inferModuleReset (#2571) (#2573) Co-authored-by: Jack Koenig (cherry picked from commit 3c6c044b6bdee850ad9ba375324abaf3813c557d) Co-authored-by: Adam Izraelevitz --- core/src/main/scala/chisel3/Module.scala | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'core/src/main/scala/chisel3/Module.scala') diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala index 3382cd1b..08286ed5 100644 --- a/core/src/main/scala/chisel3/Module.scala +++ b/core/src/main/scala/chisel3/Module.scala @@ -141,6 +141,15 @@ abstract class Module(implicit moduleCompileOptions: CompileOptions) extends Raw // Top module and compatibility mode use Bool for reset // Note that a Definition elaboration will lack a parent, but still not be a Top module val inferReset = (_parent.isDefined || Builder.inDefinition) && moduleCompileOptions.inferModuleReset + if (moduleCompileOptions.migrateInferModuleReset && !moduleCompileOptions.inferModuleReset) { + this match { + case _: RequireSyncReset => // Good! It's been migrated. + case _ => // Bad! It hasn't been migrated. + Builder.error( + s"$desiredName is not inferring its module reset, but has not been marked `RequireSyncReset`. Please extend this trait." + ) + } + } if (inferReset) Reset() else Bool() } -- cgit v1.2.3 From 13641d95951b189d7f5b0d4d99ace45f8b8f6282 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Mon, 13 Jun 2022 19:11:33 +0000 Subject: Add ImplicitInvalidate, to help migrate the explicitInvalidate compiler option (#2575) (#2579) * Added ImplicitInvalidate trait with tests (cherry picked from commit 1356ced1b89ca35ae0cb1d1ab45227ec1776d5e7) Co-authored-by: Adam Izraelevitz --- core/src/main/scala/chisel3/Module.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'core/src/main/scala/chisel3/Module.scala') diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala index 08286ed5..d03122f9 100644 --- a/core/src/main/scala/chisel3/Module.scala +++ b/core/src/main/scala/chisel3/Module.scala @@ -386,7 +386,7 @@ package internal { clonePorts.setAllParents(Some(cloneParent)) cloneParent._portsRecord = clonePorts // Normally handled during Module construction but ClonePorts really lives in its parent's parent - if (!compileOptions.explicitInvalidate) { + if (!compileOptions.explicitInvalidate || Builder.currentModule.get.isInstanceOf[ImplicitInvalidate]) { // FIXME This almost certainly doesn't work since clonePorts is not a real thing... pushCommand(DefInvalid(sourceInfo, clonePorts.ref)) } -- cgit v1.2.3 From d001b34f816f1f65d0625aebf33e5cfc5ba93e49 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Thu, 16 Jun 2022 23:15:42 +0000 Subject: Define leading '_' as API for creating temporaries (backport #2580) (#2581) * Define leading '_' as API for creating temporaries Chisel and FIRRTL have long used signals with names beginning with an underscore as an API to specify that the name does not really matter. Tools like Verilator follow a similar convention and exclude signals with underscore names from waveform dumps by default. With the introduction of compiler-plugin prefixing in Chisel 3.4, the convention remained but was hard for users to use unless the unnnamed signal existed outside of any prefix domain. Notably, unnamed signals are most useful when creating wires inside of utility methods which almost always results in the signal ending up with a prefix. With this commit, Chisel explicitly recognizes signals whos val names start with an underscore and preserve that underscore regardless of any prefixing. Chisel will also ignore such underscores when generating prefixes based on the temporary signal, preventing accidental double underscores in the names of signals that are prefixed by the temporary. (cherry picked from commit bd94366290886f3489d58f88b9768c7c11fa2cb6) * Remove unused defaultPrefix argument from _computeName (cherry picked from commit ec178aa20a830df2c8c756b9e569709a59073554) # Conflicts: # core/src/main/scala/chisel3/Module.scala # core/src/main/scala/chisel3/experimental/hierarchy/ModuleClone.scala * Resolve backport conflicts * Waive false positive binary compatibility errors Co-authored-by: Jack Koenig --- core/src/main/scala/chisel3/Module.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'core/src/main/scala/chisel3/Module.scala') diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala index d03122f9..ba2d2e32 100644 --- a/core/src/main/scala/chisel3/Module.scala +++ b/core/src/main/scala/chisel3/Module.scala @@ -275,7 +275,7 @@ package internal { private[chisel3] def setRefAndPortsRef(namespace: Namespace): Unit = { val record = _portsRecord // Use .forceName to re-use default name resolving behavior - record.forceName(None, default = this.desiredName, namespace) + record.forceName(default = this.desiredName, namespace) // Now take the Ref that forceName set and convert it to the correct Arg val instName = record.getRef match { case Ref(name) => name @@ -497,7 +497,7 @@ package experimental { private[chisel3] def namePorts(names: HashMap[HasId, String]): Unit = { for (port <- getModulePorts) { - port._computeName(None, None).orElse(names.get(port)) match { + port._computeName(None).orElse(names.get(port)) match { case Some(name) => if (_namespace.contains(name)) { Builder.error( -- cgit v1.2.3