From 6043ede715a44992975e60990fd2924b1ea6896a Mon Sep 17 00:00:00 2001 From: chick Date: Thu, 12 Dec 2019 12:06:15 -0800 Subject: Fixed problem creating Interval literals with full ranges - boundary testing was not taking binary point into account correctly - add tests to show where things work and where they are supposed to fail --- chiselFrontend/src/main/scala/chisel3/Bits.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'chiselFrontend') diff --git a/chiselFrontend/src/main/scala/chisel3/Bits.scala b/chiselFrontend/src/main/scala/chisel3/Bits.scala index 28d1690d..af13ee44 100644 --- a/chiselFrontend/src/main/scala/chisel3/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/Bits.scala @@ -2162,16 +2162,16 @@ package experimental { protected[chisel3] def Lit(value: BigInt, range: IntervalRange): Interval = { val lit = IntervalLit(value, range.getWidth, range.binaryPoint) - val bigDecimal = BigDecimal(value) + val bigDecimal = BigDecimal(value) / (1 << lit.binaryPoint.get) val inRange = (range.lowerBound, range.upperBound) match { case (firrtlir.Closed(l), firrtlir.Closed(u)) => l <= bigDecimal && bigDecimal <= u - case (firrtlir.Closed(l), firrtlir.Open(u)) => l <= bigDecimal && bigDecimal <= u - case (firrtlir.Open(l), firrtlir.Closed(u)) => l <= bigDecimal && bigDecimal <= u - case (firrtlir.Open(l), firrtlir.Open(u)) => l <= bigDecimal && bigDecimal <= u + case (firrtlir.Closed(l), firrtlir.Open(u)) => l <= bigDecimal && bigDecimal < u + case (firrtlir.Open(l), firrtlir.Closed(u)) => l < bigDecimal && bigDecimal <= u + case (firrtlir.Open(l), firrtlir.Open(u)) => l < bigDecimal && bigDecimal < u } if(! inRange) { throw new ChiselException( - s"Error literal interval value $value is not contained in specified range $range" + s"Error literal interval value $bigDecimal is not contained in specified range $range" ) } val result = Interval(range) -- cgit v1.2.3 From 98a6710cc0447d79cbd12271ea450c70e619b6f8 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Tue, 17 Dec 2019 12:41:36 -0800 Subject: Band aid until litOption is implemented for Aggregates. (#1277) This is just a band aid until an Aggregate `isLit()` method (for which work has begun) is implemented.--- chiselFrontend/src/main/scala/chisel3/Aggregate.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'chiselFrontend') diff --git a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala index 42b40ed9..8141fdba 100644 --- a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala @@ -43,7 +43,7 @@ sealed abstract class Aggregate extends Data { } } - override def litOption: Option[BigInt] = ??? // TODO implement me + override def litOption: Option[BigInt] = None // TODO implement me /** Returns a Seq of the immediate contents of this Aggregate, in order. */ -- cgit v1.2.3 From d4300b9deae6dde7ce0f314ea73a9ca4a1c3868c Mon Sep 17 00:00:00 2001 From: Leway Colin Date: Wed, 8 Jan 2020 06:25:29 +0800 Subject: Remove over design (#1237) Co-authored-by: Albert Magyar Co-authored-by: Chick Markley --- chiselFrontend/src/main/scala/chisel3/internal/Builder.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'chiselFrontend') diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index b5f617f0..c119315d 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -18,7 +18,7 @@ private[chisel3] class Namespace(keywords: Set[String]) { names(keyword) = 1 private def rename(n: String): String = { - val index = names.getOrElse(n, 1L) + val index = names(n) val tryName = s"${n}_${index}" names(n) = index + 1 if (this contains tryName) rename(n) else tryName -- cgit v1.2.3