From bb12fe7f61d12f51cf5d56b2a66aca0a1234abb3 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 15 Apr 2017 00:00:48 -0700 Subject: Fix assignment from 0-entry Vec: add test (#580) * Partially revert 8e4ddc62db448b613ae327792e72defca4d115d4 It was an incomplete fix for handling Vec(0). * Fix assignment from 0-entry Vec: add test 375e2b6a0a456c55298d82837d28986de6211ebc introduced a regression for bundles containing zero-entry Vecs. Until zero-width UInts are supported, the zero-entry Vecs need to be flattened out before doing asUInt/asTypeOf on a bundle. Undoing that commit's replacement of Data.flatten with Aggregate.getElements is the best interim fix. --- chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'chiselFrontend') diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index be874042..8143d4db 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -24,13 +24,13 @@ sealed abstract class Aggregate extends Data { pushCommand(BulkConnect(sourceInfo, this.lref, that.lref)) override def do_asUInt(implicit sourceInfo: SourceInfo): UInt = { - SeqUtils.do_asUInt(getElements.map(_.asUInt())) + SeqUtils.do_asUInt(flatten.map(_.asUInt())) } private[core] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { var i = 0 val bits = Wire(UInt(this.width), init=that) // handles width padding - for (x <- getElements) { + for (x <- flatten) { x.connectFromBits(bits(i + x.getWidth - 1, i)) i += x.getWidth } @@ -501,7 +501,6 @@ class Bundle extends Record { * be one, otherwise returns None. */ private def getBundleField(m: java.lang.reflect.Method): Option[Data] = m.invoke(this) match { - case v: Vec[_] if v.isEmpty => None case d: Data => Some(d) case Some(d: Data) => Some(d) case _ => None -- cgit v1.2.3