From 29f84617ea30c7dd30c9616bcdb9a1894b8a0762 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 15:23:25 -0800
Subject: Eliminate some doc warnings

---
 chiselFrontend/src/main/scala/chisel3/core/Binding.scala | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
index 467cb4eb..3dfde7c2 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
@@ -140,10 +140,9 @@ object Binding {
       }
     }
 
-    /** Diagnose a binding error caused by a missing IO() wrapper.
-      * @param element the element triggering the binding error.
-      * @return true if the element is a member of the module's io but ioDefined is false.
-      */
+    // Diagnose a binding error caused by a missing IO() wrapper.
+    // element is the element triggering the binding error.
+    // Returns true if the element is a member of the module's io but ioDefined is false.
     def isMissingIOWrapper(element: Element): Boolean = {
       element._parent match {
         case None => false
-- 
cgit v1.2.3


From 822160cc8e76e70643fb56707bb39f6f7526b6fd Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Thu, 22 Sep 2016 22:38:33 -0700
Subject: Add support for parameterized BlackBoxes

Also restrict black boxes to not allow hardware inside of them since it was
being silently dropped anyway.

Resolves #289
---
 .../src/main/scala/chisel3/core/BlackBox.scala         | 18 ++++++++++++------
 .../src/main/scala/chisel3/core/Module.scala           | 10 +++++++++-
 .../src/main/scala/chisel3/internal/Builder.scala      |  5 ++++-
 .../src/main/scala/chisel3/internal/firrtl/IR.scala    |  8 +++++++-
 4 files changed, 32 insertions(+), 9 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index 7fe429fa..85a57111 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -3,11 +3,20 @@
 package chisel3.core
 
 import chisel3.internal.Builder.pushCommand
-import chisel3.internal.firrtl.{ModuleIO, DefInvalid}
+import chisel3.internal.firrtl._
+import chisel3.internal.throwException
 import chisel3.internal.sourceinfo.SourceInfo
 // TODO: remove this once we have CompileOptions threaded through the macro system.
 import chisel3.core.ExplicitCompileOptions.NotStrict
 
+/** Parameters for BlackBoxes */
+sealed abstract class Param
+case class IntParam(value: BigInt) extends Param
+case class DoubleParam(value: Double) extends Param
+case class StringParam(value: String) extends Param
+/** Unquoted String */
+case class RawParam(value: String) extends Param
+
 /** Defines a black box, which is a module that can be referenced from within
   * Chisel, but is not defined in the emitted Verilog. Useful for connecting
   * to RTL modules defined outside Chisel.
@@ -16,12 +25,9 @@ import chisel3.core.ExplicitCompileOptions.NotStrict
   * {{{
   * ... to be written once a spec is finalized ...
   * }}}
+  * @note The parameters API is experimental and may change
   */
-// REVIEW TODO: make Verilog parameters part of the constructor interface?
-abstract class BlackBox extends Module {
-  // Don't bother taking override_clock|reset, clock/reset locked out anyway
-  // TODO: actually implement this.
-  def setVerilogParameters(s: String): Unit = {}
+abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param]) extends Module {
 
   // The body of a BlackBox is empty, the real logic happens in firrtl/Emitter.scala
   // Bypass standard clock, reset, io port declaration by flattening io
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index ca391091..62b6d5ce 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -41,8 +41,16 @@ object Module {
                      sourceInfo.makeMessage(" See " + _))
     }
     Builder.currentModule = parent // Back to parent!
+
     val ports = m.computePorts
-    val component = Component(m, m.name, ports, m._commands)
+    // Blackbox inherits from Module so we have to match on it first TODO fix
+    val component = m match {
+      case bb: BlackBox =>
+        DefBlackBox(bb, bb.name, ports, bb.params)
+      case mod: Module =>
+        mod._commands.prepend(DefInvalid(childSourceInfo, mod.io.ref)) // init module outputs
+        DefModule(mod, mod.name, ports, mod._commands)
+    }
     m._component = Some(component)
     Builder.components += component
     // Avoid referencing 'parent' in top module
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index 028ce628..60ce6d5d 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -181,7 +181,10 @@ private[chisel3] object Builder {
   // TODO(twigg): Ideally, binding checks and new bindings would all occur here
   // However, rest of frontend can't support this yet.
   def pushCommand[T <: Command](c: T): T = {
-    forcedModule._commands += c
+    forcedModule match {
+      case _: BlackBox => throwException("Cannot add hardware to a BlackBox")
+      case m => m._commands += c
+    }
     c
   }
   def pushOp[T <: Data](cmd: DefPrim[T]): T = {
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 0f866c27..17b869f2 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -215,8 +215,14 @@ case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
 case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command
 case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
 case class Stop(sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Command
-case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg
 case class Port(id: Data, dir: Direction)
 case class Printf(sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Command
+abstract class Component extends Arg {
+  def id: Module
+  def name: String
+  def ports: Seq[Port]
+}
+case class DefModule(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
+case class DefBlackBox(id: Module, name: String, ports: Seq[Port], params: Map[String, Param]) extends Component
 
 case class Circuit(name: String, components: Seq[Component])
-- 
cgit v1.2.3


From bb1cb894f6f1c88e0d60de1501e86d68de7c0f76 Mon Sep 17 00:00:00 2001
From: chick
Date: Wed, 9 Nov 2016 15:57:06 -0800
Subject: first attack on creating a range api for chisel3

---
 .../src/main/scala/chisel3/core/Bits.scala         |  9 ++++
 .../main/scala/chisel3/internal/firrtl/IR.scala    | 57 ++++++++++++++++++++++
 2 files changed, 66 insertions(+)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 4a09c70e..83733089 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -563,6 +563,10 @@ private[core] sealed trait UIntFactory {
     result.binding = LitBinding()
     result
   }
+   /** Create a UInt with the specified range */
+  def apply(range: Range): UInt = {
+    width(range.getWidth)
+  }
 
   /** Create a UInt with a specified width - compatibility with Chisel2. */
   // NOTE: This resolves UInt(width = 32)
@@ -728,6 +732,11 @@ object SInt {
   /** Create an SInt literal with specified width. */
   def apply(value: BigInt, width: Width): SInt = Lit(value, width)
 
+  /** Create a SInt with the specified range */
+  def apply(range: Range): SInt = {
+    width(range.getWidth)
+  }
+
   def Lit(value: BigInt): SInt = Lit(value, Width())
   def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
    /** Create an SInt literal with specified width. */
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 17b869f2..d463d78e 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -109,6 +109,63 @@ case class Index(imm: Arg, value: Arg) extends Arg {
   override def fullName(ctx: Component): String = s"${imm.fullName(ctx)}[${value.fullName(ctx)}]"
 }
 
+object Range {
+  def log2Up(value: BigInt): Int = {
+    require(value >= 0)
+    1 max (value-1).bitLength
+  }
+}
+
+/*sealed abstract class Range {
+
+}*/
+sealed trait Bound
+sealed trait NumericBound[T] extends Bound {
+  val value: T
+}
+sealed case class Open[T](value: T) extends NumericBound[T]
+sealed case class Closed[T](value: T) extends NumericBound[T]
+
+sealed trait Range {
+  val min: Bound
+  val max: Bound
+  def getWidth: Width
+}
+
+sealed trait KnownIntRange extends Range {
+  val min: NumericBound[Int]
+  val max: NumericBound[Int]
+
+  require( (min, max) match {
+    case (low, Open(high_val)) => low.value < high_val
+    case (Open(low_val), high) => low_val < high.value
+    case (Closed(low_val), Closed(high_val)) => low_val <= high_val
+  })
+}
+
+sealed case class KnownUIntRange(min: NumericBound[Int], max: NumericBound[Int]) extends KnownIntRange {
+  require (min.value >= 0)
+
+  def getWidth: Width = max match {
+    case Open(v) => Width(BigInt(v - 1).bitLength.max(1))
+    case Closed(v) => Width(BigInt(v).bitLength.max(1))
+  }
+}
+
+sealed case class KnownSIntRange(min: NumericBound[Int], max: NumericBound[Int]) extends KnownIntRange {
+
+  val maxWidth = max match {
+    case Open(v) => Width(BigInt(v - 1).bitLength + 1)
+    case Closed(v) => Width(BigInt(v).bitLength + 1)
+  }
+  val minWidth = min match {
+    case Open(v) => Width(BigInt(v + 1).bitLength + 1)
+    case Closed(v) => Width(BigInt(v).bitLength + 1)
+  }
+  def getWidth: Width = maxWidth.max(minWidth)
+
+}
+
 object Width {
   def apply(x: Int): Width = KnownWidth(x)
   def apply(): Width = UnknownWidth()
-- 
cgit v1.2.3


From 22406a589c4a3f8de42a9f5c988201f474c11282 Mon Sep 17 00:00:00 2001
From: chick
Date: Wed, 9 Nov 2016 16:23:52 -0800
Subject: simple test that range interpolator works with UInt factory method

---
 chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 83733089..82b60a4c 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -563,10 +563,14 @@ private[core] sealed trait UIntFactory {
     result.binding = LitBinding()
     result
   }
-   /** Create a UInt with the specified range */
+  /** Create a UInt with the specified range */
   def apply(range: Range): UInt = {
     width(range.getWidth)
   }
+  /** Create a UInt with the specified range */
+  def apply(range: (NumericBound[Int], NumericBound[Int])): UInt = {
+    apply(KnownUIntRange(range._1, range._2))
+  }
 
   /** Create a UInt with a specified width - compatibility with Chisel2. */
   // NOTE: This resolves UInt(width = 32)
@@ -736,6 +740,10 @@ object SInt {
   def apply(range: Range): SInt = {
     width(range.getWidth)
   }
+  /** Create a SInt with the specified range */
+  def apply(range: (NumericBound[Int], NumericBound[Int])): SInt = {
+    apply(KnownSIntRange(range._1, range._2))
+  }
 
   def Lit(value: BigInt): SInt = Lit(value, Width())
   def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
-- 
cgit v1.2.3


From 876bc32feca6bd0a2aaec7019fd3d29675ce0255 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 15:23:36 -0800
Subject: Fix open-open range specifier, remove dead code, restyle tests

---
 .../src/main/scala/chisel3/internal/firrtl/IR.scala       | 15 +++------------
 1 file changed, 3 insertions(+), 12 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index d463d78e..262b939f 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -109,16 +109,6 @@ case class Index(imm: Arg, value: Arg) extends Arg {
   override def fullName(ctx: Component): String = s"${imm.fullName(ctx)}[${value.fullName(ctx)}]"
 }
 
-object Range {
-  def log2Up(value: BigInt): Int = {
-    require(value >= 0)
-    1 max (value-1).bitLength
-  }
-}
-
-/*sealed abstract class Range {
-
-}*/
 sealed trait Bound
 sealed trait NumericBound[T] extends Bound {
   val value: T
@@ -137,8 +127,9 @@ sealed trait KnownIntRange extends Range {
   val max: NumericBound[Int]
 
   require( (min, max) match {
-    case (low, Open(high_val)) => low.value < high_val
-    case (Open(low_val), high) => low_val < high.value
+    case (Open(low_val), Open(high_val)) => low_val < high_val - 1
+    case (Closed(low_val), Open(high_val)) => low_val < high_val
+    case (Open(low_val), Closed(high_val)) => low_val < high_val
     case (Closed(low_val), Closed(high_val)) => low_val <= high_val
   })
 }
-- 
cgit v1.2.3


From 15a8d3818a1b185051b260ffc82da1fb4a60a45e Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 18:31:24 -0800
Subject: Break out deprecated literal constructors, refactor all the things!

---
 .../src/main/scala/chisel3/core/Aggregate.scala    | 10 ++--
 .../src/main/scala/chisel3/core/Bits.scala         | 69 ++++++----------------
 .../src/main/scala/chisel3/core/Mem.scala          |  2 +-
 .../src/main/scala/chisel3/core/SeqUtils.scala     |  4 +-
 .../src/main/scala/chisel3/core/package.scala      | 50 ++++++++++++++++
 5 files changed, 76 insertions(+), 59 deletions(-)
 create mode 100644 chiselFrontend/src/main/scala/chisel3/core/package.scala

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index de7af462..77a1b57a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -123,10 +123,10 @@ object Vec {
   /** Truncate an index to implement modulo-power-of-2 addressing. */
   private[core] def truncateIndex(idx: UInt, n: Int)(implicit sourceInfo: SourceInfo): UInt = {
     val w = BigInt(n-1).bitLength
-    if (n <= 1) UInt(0)
+    if (n <= 1) 0.U
     else if (idx.width.known && idx.width.get <= w) idx
     else if (idx.width.known) idx(w-1,0)
-    else (idx | UInt(0, w))(w-1,0)
+    else (idx | 0.U(w))(w-1,0)
   }
 }
 
@@ -249,7 +249,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
   // IndexedSeq has its own hashCode/equals that we must not use
   override def hashCode: Int = super[HasId].hashCode
   override def equals(that: Any): Boolean = super[HasId].equals(that)
-  
+
   @deprecated("Use Vec.apply instead", "chisel3")
   def read(idx: UInt): T
 
@@ -288,7 +288,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
   /** Helper function that appends an index (literal value) to each element,
     * useful for hardware generators which output an index.
     */
-  private def indexWhereHelper(p: T => Bool) = this map p zip (0 until length).map(i => UInt(i))
+  private def indexWhereHelper(p: T => Bool) = this map p zip (0 until length).map(i => i.asUInt)
 
   /** Outputs the index of the first element for which p outputs true.
     */
@@ -388,7 +388,7 @@ class Bundle extends Aggregate {
   private[chisel3] lazy val flatten = namedElts.flatMap(_._2.flatten)
   private[chisel3] override def _onModuleClose: Unit = // scalastyle:ignore method.name
     for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) }
-    
+
   private[chisel3] final def allElements: Seq[Element] = namedElts.flatMap(_._2.allElements)
 
   override def cloneType : this.type = {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 82b60a4c..1d3f9243 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -134,7 +134,7 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
     }
     val w = x - y + 1
     if (isLit()) {
-      UInt((litValue >> y) & ((BigInt(1) << w) - 1), w)
+      ((litValue >> y) & ((BigInt(1) << w) - 1)).asUInt(w)
     } else {
       Binding.checkSynthesizable(this, s"'this' ($this)")
       pushOp(DefPrim(sourceInfo, UInt(Width(w)), BitsExtractOp, this.ref, ILit(x), ILit(y)))
@@ -304,11 +304,6 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
   final def toPrintable: Printable = Decimal(this)
 }
 
-/** Provides a set of operations to create UInt types and literals.
-  * Identical in functionality to the UInt companion object.
-  */
-object Bits extends UIntFactory
-
 // REVIEW TODO: Further discussion needed on what Num actually is.
 /** Abstract trait defining operations available on numeric-like wire data
   * types.
@@ -408,14 +403,14 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
   private[chisel3] def toType = s"UInt$width"
 
   override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
-    UInt(value, width).asInstanceOf[this.type]
+    value.asUInt(width).asInstanceOf[this.type]
 
   // TODO: refactor to share documentation with Num or add independent scaladoc
   final def unary_- (): UInt = macro SourceInfoTransform.noArg
   final def unary_-% (): UInt = macro SourceInfoTransform.noArg
 
-  def do_unary_- (implicit sourceInfo: SourceInfo) : UInt = UInt(0) - this
-  def do_unary_-% (implicit sourceInfo: SourceInfo): UInt = UInt(0) -% this
+  def do_unary_- (implicit sourceInfo: SourceInfo) : UInt = 0.U - this
+  def do_unary_-% (implicit sourceInfo: SourceInfo): UInt = 0.U -% this
 
   override def do_+ (that: UInt)(implicit sourceInfo: SourceInfo): UInt = this +% that
   override def do_- (that: UInt)(implicit sourceInfo: SourceInfo): UInt = this -% that
@@ -463,8 +458,8 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
   final def andR(): Bool = macro SourceInfoTransform.noArg
   final def xorR(): Bool = macro SourceInfoTransform.noArg
 
-  def do_orR(implicit sourceInfo: SourceInfo): Bool = this != UInt(0)
-  def do_andR(implicit sourceInfo: SourceInfo): Bool = ~this === UInt(0)
+  def do_orR(implicit sourceInfo: SourceInfo): Bool = this != 0.U
+  def do_andR(implicit sourceInfo: SourceInfo): Bool = ~this === 0.U
   def do_xorR(implicit sourceInfo: SourceInfo): Bool = redop(sourceInfo, XorReduceOp)
 
   override def do_< (that: UInt)(implicit sourceInfo: SourceInfo): Bool = compop(sourceInfo, LessOp, that)
@@ -483,7 +478,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
 
   final def unary_! () : Bool = macro SourceInfoTransform.noArg
 
-  def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === UInt(0, 1)
+  def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === 0.U(1)
 
   override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): UInt =
     binop(sourceInfo, UInt(this.width + that), ShiftLeftOp, that)
@@ -501,7 +496,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
   final def bitSet(off: UInt, dat: Bool): UInt = macro UIntTransform.bitset
 
   def do_bitSet(off: UInt, dat: Bool)(implicit sourceInfo: SourceInfo): UInt = {
-    val bit = UInt(1, 1) << off
+    val bit = 1.U(1) << off
     Mux(dat, this | bit, ~(~this | bit))
   }
 
@@ -532,31 +527,20 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
 }
 
 // This is currently a factory because both Bits and UInt inherit it.
-private[core] sealed trait UIntFactory {
+trait UIntFactory {
   /** Create a UInt type with inferred width. */
   def apply(): UInt = apply(Width())
   /** Create a UInt port with specified width. */
   def apply(width: Width): UInt = new UInt(width)
-  /** Create a UInt with a specified width - compatibility with Chisel2. */
-  def width(width: Int): UInt = apply(Width(width))
-  /** Create a UInt port with specified width. */
-  def width(width: Width): UInt = new UInt(width)
-  /** Create a UInt literal with fixed width. */
-  def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
-  /** Create a UInt literal with inferred width. */
-  def apply(n: String): UInt = Lit(n)
-   /** Create a UInt literal with fixed width. */
-  def apply(n: String, width: Int): UInt = Lit(parse(n), width)
-  /** Create a UInt literal with specified width. */
-  def apply(value: BigInt, width: Width): UInt = Lit(value, width)
-  def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width))
+
+  protected[chisel3] def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width))
    /** Create a UInt literal with inferred width. */
-  def Lit(value: BigInt): UInt = Lit(value, Width())
-  def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n))
+  protected[chisel3] def Lit(value: BigInt): UInt = Lit(value, Width())
+  protected[chisel3] def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n))
    /** Create a UInt literal with fixed width. */
-  def Lit(n: String, width: Int): UInt = Lit(parse(n), width)
+  protected[chisel3] def Lit(n: String, width: Int): UInt = Lit(parse(n), width)
    /** Create a UInt literal with specified width. */
-  def Lit(value: BigInt, width: Width): UInt = {
+  protected[chisel3] def Lit(value: BigInt, width: Width): UInt = {
     val lit = ULit(value, width)
     val result = new UInt(lit.width, Some(lit))
     // Bind result to being an Literal
@@ -572,25 +556,7 @@ private[core] sealed trait UIntFactory {
     apply(KnownUIntRange(range._1, range._2))
   }
 
-  /** Create a UInt with a specified width - compatibility with Chisel2. */
-  // NOTE: This resolves UInt(width = 32)
-  def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
-  /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
-  def apply(value: BigInt): UInt = apply(value, Width())
-  /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
-  def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width))
-  /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
-  def apply(dir: Direction): UInt = apply(dir, Width())
-  def apply(dir: Direction, wWidth: Width): UInt = {
-    val result = apply(wWidth)
-    dir match {
-      case Direction.Input => Input(result)
-      case Direction.Output => Output(result)
-      case Direction.Unspecified => result
-    }
-  }
-
-  private def parse(n: String) = {
+  protected def parse(n: String) = {
     val (base, num) = n.splitAt(1)
     val radix = base match {
       case "x" | "h" => 16
@@ -602,7 +568,7 @@ private[core] sealed trait UIntFactory {
     BigInt(num.filterNot(_ == '_'), radix)
   }
 
-  private def parsedWidth(n: String) =
+  protected def parsedWidth(n: String) =
     if (n(0) == 'b') {
       Width(n.length-1)
     } else if (n(0) == 'h') {
@@ -613,6 +579,7 @@ private[core] sealed trait UIntFactory {
 }
 
 object UInt extends UIntFactory
+object Bits extends UIntFactory
 
 sealed class SInt private (width: Width, lit: Option[SLit] = None)
     extends Bits(width, lit) with Num[SInt] {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index a43b19fe..1863e921 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -40,7 +40,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
     */
   def apply(idx: Int): T = {
     require(idx >= 0 && idx < length)
-    apply(UInt(idx))
+    apply(idx.asUInt)
   }
 
   /** Creates a read/write accessor into the memory with dynamic addressing.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
index 558dea7a..da4f2d94 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
@@ -30,7 +30,7 @@ private[chisel3] object SeqUtils {
   def count(in: Seq[Bool]): UInt = macro SourceInfoTransform.inArg
 
   def do_count(in: Seq[Bool])(implicit sourceInfo: SourceInfo): UInt = in.size match {
-    case 0 => UInt(0)
+    case 0 => 0.U
     case 1 => in.head
     case n => count(in take n/2) +& count(in drop n/2)
   }
@@ -57,7 +57,7 @@ private[chisel3] object SeqUtils {
     if (in.tail.isEmpty) {
       in.head._2
     } else {
-      val masked = for ((s, i) <- in) yield Mux(s, i.asUInt, UInt(0))
+      val masked = for ((s, i) <- in) yield Mux(s, i.asUInt, 0.U)
       val width = in.map(_._2.width).reduce(_ max _)
       in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_))
     }
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
new file mode 100644
index 00000000..46dfbe20
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -0,0 +1,50 @@
+package chisel3 {
+  package object core {
+    import internal.firrtl.Width
+
+    /**
+    * These implicit classes allow one to convert scala.Int|scala.BigInt to
+    * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
+    * The versions .asUInt(width)|.asSInt(width) are also available to explicitly
+    * mark a width for the new literal.
+    *
+    * Also provides .asBool to scala.Boolean and .asUInt to String
+    *
+    * Note that, for stylistic reasons, one should avoid extracting immediately
+    * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
+    * confusion (the 1 is a bit length and the 0 is a bit extraction position).
+    * Prefer storing the result and then extracting from it.
+    */
+    implicit class fromIntToLiteral(val x: Int) {
+      def U: UInt = UInt.Lit(BigInt(x), Width())    // scalastyle:ignore method.name
+      def S: SInt = SInt(BigInt(x), Width())    // scalastyle:ignore method.name
+
+      def asUInt(): UInt = UInt.Lit(x, Width())
+      def asSInt(): SInt = SInt(x, Width())
+      def asUInt(width: Int): UInt = UInt.Lit(x, width)
+      def asSInt(width: Int): SInt = SInt(x, width)
+    }
+
+    implicit class fromBigIntToLiteral(val x: BigInt) {
+      def U: UInt = UInt.Lit(x, Width())       // scalastyle:ignore method.name
+      def S: SInt = SInt(x, Width())       // scalastyle:ignore method.name
+
+      def asUInt(): UInt = UInt.Lit(x, Width())
+      def asSInt(): SInt = SInt(x, Width())
+      def asUInt(width: Int): UInt = UInt.Lit(x, width)
+      def asSInt(width: Int): SInt = SInt(x, width)
+    }
+
+    implicit class fromStringToLiteral(val x: String) {
+      def U: UInt = UInt.Lit(x)       // scalastyle:ignore method.name
+    }
+
+    implicit class fromBooleanToLiteral(val x: Boolean) {
+      def B: Bool = Bool(x)       // scalastyle:ignore method.name
+    }
+
+    implicit class fromDoubleToLiteral(val x: Double) {
+      def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint)
+    }
+  }
+}
\ No newline at end of file
-- 
cgit v1.2.3


From e0b277a40693476247a68e7c52672b547d7ceb17 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 18:47:36 -0800
Subject: Deprecate things, split more things

---
 .../src/main/scala/chisel3/core/Bits.scala         | 30 ++------------------
 .../src/main/scala/chisel3/core/package.scala      | 33 +++++++++++++++++++---
 2 files changed, 31 insertions(+), 32 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 1d3f9243..70da27fc 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -533,12 +533,6 @@ trait UIntFactory {
   /** Create a UInt port with specified width. */
   def apply(width: Width): UInt = new UInt(width)
 
-  protected[chisel3] def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width))
-   /** Create a UInt literal with inferred width. */
-  protected[chisel3] def Lit(value: BigInt): UInt = Lit(value, Width())
-  protected[chisel3] def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n))
-   /** Create a UInt literal with fixed width. */
-  protected[chisel3] def Lit(n: String, width: Int): UInt = Lit(parse(n), width)
    /** Create a UInt literal with specified width. */
   protected[chisel3] def Lit(value: BigInt, width: Width): UInt = {
     val lit = ULit(value, width)
@@ -547,35 +541,15 @@ trait UIntFactory {
     result.binding = LitBinding()
     result
   }
+
   /** Create a UInt with the specified range */
   def apply(range: Range): UInt = {
-    width(range.getWidth)
+    apply(range.getWidth)
   }
   /** Create a UInt with the specified range */
   def apply(range: (NumericBound[Int], NumericBound[Int])): UInt = {
     apply(KnownUIntRange(range._1, range._2))
   }
-
-  protected def parse(n: String) = {
-    val (base, num) = n.splitAt(1)
-    val radix = base match {
-      case "x" | "h" => 16
-      case "d" => 10
-      case "o" => 8
-      case "b" => 2
-      case _ => Builder.error(s"Invalid base $base"); 2
-    }
-    BigInt(num.filterNot(_ == '_'), radix)
-  }
-
-  protected def parsedWidth(n: String) =
-    if (n(0) == 'b') {
-      Width(n.length-1)
-    } else if (n(0) == 'h') {
-      Width((n.length-1) * 4)
-    } else {
-      Width()
-    }
 }
 
 object UInt extends UIntFactory
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 46dfbe20..554e6238 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -1,4 +1,6 @@
 package chisel3 {
+  import internal.Builder
+
   package object core {
     import internal.firrtl.Width
 
@@ -21,8 +23,8 @@ package chisel3 {
 
       def asUInt(): UInt = UInt.Lit(x, Width())
       def asSInt(): SInt = SInt(x, Width())
-      def asUInt(width: Int): UInt = UInt.Lit(x, width)
-      def asSInt(width: Int): SInt = SInt(x, width)
+      def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
+      def asSInt(width: Int): SInt = SInt(x, Width(width))
     }
 
     implicit class fromBigIntToLiteral(val x: BigInt) {
@@ -31,12 +33,35 @@ package chisel3 {
 
       def asUInt(): UInt = UInt.Lit(x, Width())
       def asSInt(): SInt = SInt(x, Width())
-      def asUInt(width: Int): UInt = UInt.Lit(x, width)
+      def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
       def asSInt(width: Int): SInt = SInt(x, width)
     }
 
     implicit class fromStringToLiteral(val x: String) {
-      def U: UInt = UInt.Lit(x)       // scalastyle:ignore method.name
+      def U: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))       // scalastyle:ignore method.name
+    }
+
+    object fromStringToLiteral {
+      def parse(n: String) = {
+        val (base, num) = n.splitAt(1)
+        val radix = base match {
+          case "x" | "h" => 16
+          case "d" => 10
+          case "o" => 8
+          case "b" => 2
+          case _ => Builder.error(s"Invalid base $base"); 2
+        }
+        BigInt(num.filterNot(_ == '_'), radix)
+      }
+
+      def parsedWidth(n: String) =
+        if (n(0) == 'b') {
+          Width(n.length-1)
+        } else if (n(0) == 'h') {
+          Width((n.length-1) * 4)
+        } else {
+          Width()
+        }
     }
 
     implicit class fromBooleanToLiteral(val x: Boolean) {
-- 
cgit v1.2.3


From 9e32a39bda3fba11e6b0990e6ad5e7e17b5d8364 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 18:54:44 -0800
Subject: Refactor SInt WIP

---
 .../src/main/scala/chisel3/core/Bits.scala         | 36 +++-------------------
 1 file changed, 4 insertions(+), 32 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 70da27fc..7e467b88 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -555,7 +555,7 @@ trait UIntFactory {
 object UInt extends UIntFactory
 object Bits extends UIntFactory
 
-sealed class SInt private (width: Width, lit: Option[SLit] = None)
+sealed class SInt private[core] (width: Width, lit: Option[SLit] = None)
     extends Bits(width, lit) with Num[SInt] {
 
   private[core] override def cloneTypeWidth(w: Width): this.type =
@@ -659,37 +659,23 @@ sealed class SInt private (width: Width, lit: Option[SLit] = None)
   }
 }
 
-object SInt {
+trait SIntFactory {
   /** Create an SInt type with inferred width. */
   def apply(): SInt = apply(Width())
   /** Create a SInt type or port with fixed width. */
   def apply(width: Width): SInt = new SInt(width)
-  /** Create a SInt type or port with fixed width. */
-  def width(width: Int): SInt = apply(Width(width))
-  /** Create an SInt type with specified width. */
-  def width(width: Width): SInt = new SInt(width)
-
-  /** Create an SInt literal with inferred width. */
-  def apply(value: BigInt): SInt = Lit(value)
-  /** Create an SInt literal with fixed width. */
-  def apply(value: BigInt, width: Int): SInt = Lit(value, width)
-
-  /** Create an SInt literal with specified width. */
-  def apply(value: BigInt, width: Width): SInt = Lit(value, width)
 
   /** Create a SInt with the specified range */
   def apply(range: Range): SInt = {
-    width(range.getWidth)
+    apply(range.getWidth)
   }
   /** Create a SInt with the specified range */
   def apply(range: (NumericBound[Int], NumericBound[Int])): SInt = {
     apply(KnownSIntRange(range._1, range._2))
   }
 
-  def Lit(value: BigInt): SInt = Lit(value, Width())
-  def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
    /** Create an SInt literal with specified width. */
-  def Lit(value: BigInt, width: Width): SInt = {
+  protected def Lit(value: BigInt, width: Width): SInt = {
 
     val lit = SLit(value, width)
     val result = new SInt(lit.width, Some(lit))
@@ -697,20 +683,6 @@ object SInt {
     result.binding = LitBinding()
     result
   }
-  /** Create a SInt with a specified width - compatibility with Chisel2. */
-  def apply(dir: Option[Direction] = None, width: Int): SInt = apply(Width(width))
-  /** Create a SInt with a specified direction and width - compatibility with Chisel2. */
-  def apply(dir: Direction, width: Int): SInt = apply(dir, Width(width))
-  /** Create a SInt with a specified direction, but unspecified width - compatibility with Chisel2. */
-  def apply(dir: Direction): SInt = apply(dir, Width())
-  def apply(dir: Direction, wWidth: Width): SInt = {
-    val result = apply(wWidth)
-    dir match {
-      case Direction.Input => Input(result)
-      case Direction.Output => Output(result)
-      case Direction.Unspecified => result
-    }
-  }
 }
 
 // REVIEW TODO: Why does this extend UInt and not Bits? Does defining airth
-- 
cgit v1.2.3


From b0cc0c93a80aec5bed54cfb11923636c09b7e180 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 11:21:59 -0800
Subject: SInt conversion finished, everything builds again

---
 .../src/main/scala/chisel3/core/Bits.scala         | 17 +++---
 .../src/main/scala/chisel3/core/package.scala      | 65 ++++++++++++++++++----
 2 files changed, 63 insertions(+), 19 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 7e467b88..aa73abf5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -134,7 +134,7 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
     }
     val w = x - y + 1
     if (isLit()) {
-      ((litValue >> y) & ((BigInt(1) << w) - 1)).asUInt(w)
+      ((litValue >> y) & ((BigInt(1) << w) - 1)).asUInt(w.W)
     } else {
       Binding.checkSynthesizable(this, s"'this' ($this)")
       pushOp(DefPrim(sourceInfo, UInt(Width(w)), BitsExtractOp, this.ref, ILit(x), ILit(y)))
@@ -403,7 +403,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
   private[chisel3] def toType = s"UInt$width"
 
   override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
-    value.asUInt(width).asInstanceOf[this.type]
+    value.asUInt(width.W).asInstanceOf[this.type]
 
   // TODO: refactor to share documentation with Num or add independent scaladoc
   final def unary_- (): UInt = macro SourceInfoTransform.noArg
@@ -563,13 +563,13 @@ sealed class SInt private[core] (width: Width, lit: Option[SLit] = None)
   private[chisel3] def toType = s"SInt$width"
 
   override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
-    SInt(value, width).asInstanceOf[this.type]
+    value.asSInt(width.W).asInstanceOf[this.type]
 
   final def unary_- (): SInt = macro SourceInfoTransform.noArg
   final def unary_-% (): SInt = macro SourceInfoTransform.noArg
 
-  def unary_- (implicit sourceInfo: SourceInfo): SInt = SInt(0) - this
-  def unary_-% (implicit sourceInfo: SourceInfo): SInt = SInt(0) -% this
+  def unary_- (implicit sourceInfo: SourceInfo): SInt = 0.S - this
+  def unary_-% (implicit sourceInfo: SourceInfo): SInt = 0.S -% this
 
   /** add (default - no growth) operator */
   override def do_+ (that: SInt)(implicit sourceInfo: SourceInfo): SInt =
@@ -637,7 +637,7 @@ sealed class SInt private[core] (width: Width, lit: Option[SLit] = None)
 
   final def abs(): UInt = macro SourceInfoTransform.noArg
 
-  def do_abs(implicit sourceInfo: SourceInfo): UInt = Mux(this < SInt(0), (-this).asUInt, this.asUInt)
+  def do_abs(implicit sourceInfo: SourceInfo): UInt = Mux(this < 0.S, (-this).asUInt, this.asUInt)
 
   override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): SInt =
     binop(sourceInfo, SInt(this.width + that), ShiftLeftOp, that)
@@ -675,8 +675,7 @@ trait SIntFactory {
   }
 
    /** Create an SInt literal with specified width. */
-  protected def Lit(value: BigInt, width: Width): SInt = {
-
+  protected[chisel3] def Lit(value: BigInt, width: Width): SInt = {
     val lit = SLit(value, width)
     val result = new SInt(lit.width, Some(lit))
     // Bind result to being an Literal
@@ -685,6 +684,8 @@ trait SIntFactory {
   }
 }
 
+object SInt extends SIntFactory
+
 // REVIEW TODO: Why does this extend UInt and not Bits? Does defining airth
 // operations on a Bool make sense?
 /** A data type for booleans, defined as a single bit indicating true or false.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 554e6238..7fb05c75 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -18,23 +18,62 @@ package chisel3 {
     * Prefer storing the result and then extracting from it.
     */
     implicit class fromIntToLiteral(val x: Int) {
-      def U: UInt = UInt.Lit(BigInt(x), Width())    // scalastyle:ignore method.name
-      def S: SInt = SInt(BigInt(x), Width())    // scalastyle:ignore method.name
+      /** Int to UInt conversion, recommended style for constants.
+        */
+      def U: UInt = UInt.Lit(BigInt(x), Width())  // scalastyle:ignore method.name
+      /** Int to SInt conversion, recommended style for constants.
+        */
+      def S: SInt = SInt.Lit(BigInt(x), Width())  // scalastyle:ignore method.name
 
+      /** Int to UInt conversion, recommended style for variables.
+        */
       def asUInt(): UInt = UInt.Lit(x, Width())
-      def asSInt(): SInt = SInt(x, Width())
-      def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
-      def asSInt(width: Int): SInt = SInt(x, Width(width))
+      /** Int to SInt conversion, recommended style for variables.
+        */
+      def asSInt(): SInt = SInt.Lit(x, Width())
+      /** Int to UInt conversion with specified width, recommended style for variables.
+        */
+      def asUInt(width: Width): UInt = UInt.Lit(x, width)
+      /** Int to SInt conversion with specified width, recommended style for variables.
+        */
+      def asSInt(width: Width): SInt = SInt.Lit(x, width)
+
+      /** Int to UInt conversion with specified width, recommended style for variables.
+        */
+      //def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
+      /** Int to SInt conversion with specified width, recommended style for variables.
+        */
+      //def asSInt(width: Int): SInt = SInt(x, Width(width))
+
     }
 
     implicit class fromBigIntToLiteral(val x: BigInt) {
-      def U: UInt = UInt.Lit(x, Width())       // scalastyle:ignore method.name
-      def S: SInt = SInt(x, Width())       // scalastyle:ignore method.name
+      /** Int to UInt conversion, recommended style for constants.
+        */
+      def U: UInt = UInt.Lit(x, Width())  // scalastyle:ignore method.name
+      /** Int to SInt conversion, recommended style for constants.
+        */
+      def S: SInt = SInt.Lit(x, Width())  // scalastyle:ignore method.name
 
+      /** Int to UInt conversion, recommended style for variables.
+        */
       def asUInt(): UInt = UInt.Lit(x, Width())
-      def asSInt(): SInt = SInt(x, Width())
-      def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
-      def asSInt(width: Int): SInt = SInt(x, width)
+      /** Int to SInt conversion, recommended style for variables.
+        */
+      def asSInt(): SInt = SInt.Lit(x, Width())
+      /** Int to UInt conversion with specified width, recommended style for variables.
+        */
+      def asUInt(width: Width): UInt = UInt.Lit(x, width)
+      /** Int to SInt conversion with specified width, recommended style for variables.
+        */
+      def asSInt(width: Width): SInt = SInt.Lit(x, width)
+
+      /** Int to UInt conversion with specified width, recommended style for variables.
+        */
+      // def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
+      /** Int to SInt conversion with specified width, recommended style for variables.
+        */
+      // def asSInt(width: Int): SInt = SInt(x, width)
     }
 
     implicit class fromStringToLiteral(val x: String) {
@@ -65,11 +104,15 @@ package chisel3 {
     }
 
     implicit class fromBooleanToLiteral(val x: Boolean) {
-      def B: Bool = Bool(x)       // scalastyle:ignore method.name
+      def B: Bool = Bool(x)  // scalastyle:ignore method.name
     }
 
     implicit class fromDoubleToLiteral(val x: Double) {
       def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint)
     }
+
+    implicit class fromIntToWidth(val x: Int) {
+      def W: Width = Width(x)  // scalastyle:ignore method.name
+    }
   }
 }
\ No newline at end of file
-- 
cgit v1.2.3


From cd904da0aa0e96ba679906a3ee5dbdc068eace48 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 11:33:20 -0800
Subject: Restyle Bool constructors, move compatibility deprecations into
 compatibility package object

---
 .../src/main/scala/chisel3/core/Aggregate.scala      |  4 ++--
 .../src/main/scala/chisel3/core/Bits.scala           | 20 ++++++--------------
 .../src/main/scala/chisel3/core/package.scala        |  8 +++++++-
 3 files changed, 15 insertions(+), 17 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 77a1b57a..8fdcb260 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -261,14 +261,14 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
   def forall(p: T => Bool): Bool = macro SourceInfoTransform.pArg
 
   def do_forall(p: T => Bool)(implicit sourceInfo: SourceInfo): Bool =
-    (this map p).fold(Bool(true))(_ && _)
+    (this map p).fold(true.B)(_ && _)
 
   /** Outputs true if p outputs true for at least one element.
     */
   def exists(p: T => Bool): Bool = macro SourceInfoTransform.pArg
 
   def do_exists(p: T => Bool)(implicit sourceInfo: SourceInfo): Bool =
-    (this map p).fold(Bool(false))(_ || _)
+    (this map p).fold(false.B)(_ || _)
 
   /** Outputs true if the vector contains at least one element equal to x (using
     * the === operator).
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index aa73abf5..b81679b6 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -92,7 +92,7 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
       Builder.error(s"Negative bit indices are illegal (got $x)")
     }
     if (isLit()) {
-      Bool(((litValue() >> x.toInt) & 1) == 1)
+      (((litValue() >> x.toInt) & 1) == 1).asBool
     } else {
       Binding.checkSynthesizable(this, s"'this' ($this)")
       pushOp(DefPrim(sourceInfo, Bool(), BitsExtractOp, this.ref, ILit(x), ILit(x)))
@@ -698,7 +698,7 @@ sealed class Bool(lit: Option[ULit] = None) extends UInt(Width(1), lit) {
 
   override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = {
     require((value == 0 || value == 1) && width == 1)
-    Bool(value == 1).asInstanceOf[this.type]
+    (value == 1).asBool.asInstanceOf[this.type]
   }
 
   // REVIEW TODO: Why does this need to exist and have different conventions
@@ -736,31 +736,23 @@ sealed class Bool(lit: Option[ULit] = None) extends UInt(Width(1), lit) {
   def do_asClock(implicit sourceInfo: SourceInfo): Clock = pushOp(DefPrim(sourceInfo, Clock(), AsClockOp, ref))
 }
 
-object Bool {
+trait BoolFactory {
   /** Creates an empty Bool.
    */
   def apply(): Bool = new Bool()
 
   /** Creates Bool literal.
    */
-  def apply(x: Boolean): Bool = Lit(x)
-  def Lit(x: Boolean): Bool = {
+  protected[chisel3] def Lit(x: Boolean): Bool = {
     val result = new Bool(Some(ULit(if (x) 1 else 0, Width(1))))
     // Bind result to being an Literal
     result.binding = LitBinding()
     result
   }
-  /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
-  def apply(dir: Direction): Bool = {
-    val result = apply()
-    dir match {
-      case Direction.Input => Input(result)
-      case Direction.Output => Output(result)
-      case Direction.Unspecified => result
-    }
-  }
 }
 
+object Bool extends BoolFactory
+
 object Mux {
   /** Creates a mux, whose output is one of the inputs depending on the
     * value of the condition.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 7fb05c75..ac10a140 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -104,7 +104,13 @@ package chisel3 {
     }
 
     implicit class fromBooleanToLiteral(val x: Boolean) {
-      def B: Bool = Bool(x)  // scalastyle:ignore method.name
+      /** Boolean to Bool conversion, recommended style for constants.
+        */
+      def B: Bool = Bool.Lit(x)  // scalastyle:ignore method.name
+
+      /** Boolean to Bool conversion, recommended style for variables.
+        */
+      def asBool: Bool = Bool.Lit(x)
     }
 
     implicit class fromDoubleToLiteral(val x: Double) {
-- 
cgit v1.2.3


From 54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:01:03 -0800
Subject: Restyle a lot of test code, mainly with regex

---
 chiselFrontend/src/main/scala/chisel3/core/Bits.scala  |  4 ++--
 .../src/main/scala/chisel3/core/SeqUtils.scala         |  2 +-
 chiselFrontend/src/main/scala/chisel3/core/When.scala  |  4 ++--
 .../src/main/scala/chisel3/core/package.scala          | 18 ++++++++++++++++++
 4 files changed, 23 insertions(+), 5 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index b81679b6..354512e1 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -690,7 +690,7 @@ object SInt extends SIntFactory
 // operations on a Bool make sense?
 /** A data type for booleans, defined as a single bit indicating true or false.
   */
-sealed class Bool(lit: Option[ULit] = None) extends UInt(Width(1), lit) {
+sealed class Bool(lit: Option[ULit] = None) extends UInt(1.W, lit) {
   private[core] override def cloneTypeWidth(w: Width): this.type = {
     require(!w.known || w.get == 1)
     new Bool().asInstanceOf[this.type]
@@ -762,7 +762,7 @@ object Mux {
     * @param alt the value chosen when `cond` is false
     * @example
     * {{{
-    * val muxOut = Mux(data_in === UInt(3), UInt(3, 4), UInt(0, 4))
+    * val muxOut = Mux(data_in === 3.U, 3.U(4.W), 0.U(4.W))
     * }}}
     */
   def apply[T <: Data](cond: Bool, con: T, alt: T): T = macro MuxTransform.apply[T]
diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
index da4f2d94..e435860e 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
@@ -25,7 +25,7 @@ private[chisel3] object SeqUtils {
     }
   }
 
-  /** Outputs the number of elements that === Bool(true).
+  /** Outputs the number of elements that === true.B.
     */
   def count(in: Seq[Bool]): UInt = macro SourceInfoTransform.inArg
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/When.scala b/chiselFrontend/src/main/scala/chisel3/core/When.scala
index 196e7903..7501ebb1 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/When.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/When.scala
@@ -18,9 +18,9 @@ object when {  // scalastyle:ignore object.name
     *
     * @example
     * {{{
-    * when ( myData === UInt(3) ) {
+    * when ( myData === 3.U ) {
     *   // Some logic to run when myData equals 3.
-    * } .elsewhen ( myData === UInt(1) ) {
+    * } .elsewhen ( myData === 1.U ) {
     *   // Some logic to run when myData equals 1.
     * } .otherwise {
     *   // Some logic to run when myData is neither 3 nor 1.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index ac10a140..cae64df6 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -24,6 +24,12 @@ package chisel3 {
       /** Int to SInt conversion, recommended style for constants.
         */
       def S: SInt = SInt.Lit(BigInt(x), Width())  // scalastyle:ignore method.name
+      /** Int to UInt conversion with specified width, recommended style for constants.
+        */
+      def U(width: Width): UInt = UInt.Lit(BigInt(x), width)  // scalastyle:ignore method.name
+      /** Int to SInt conversion with specified width, recommended style for constants.
+        */
+      def S(width: Width): SInt = SInt.Lit(BigInt(x), width)  // scalastyle:ignore method.name
 
       /** Int to UInt conversion, recommended style for variables.
         */
@@ -54,6 +60,12 @@ package chisel3 {
       /** Int to SInt conversion, recommended style for constants.
         */
       def S: SInt = SInt.Lit(x, Width())  // scalastyle:ignore method.name
+      /** Int to UInt conversion with specified width, recommended style for constants.
+        */
+      def U(width: Width): UInt = UInt.Lit(x, width)  // scalastyle:ignore method.name
+      /** Int to SInt conversion with specified width, recommended style for constants.
+        */
+      def S(width: Width): SInt = SInt.Lit(x, width)  // scalastyle:ignore method.name
 
       /** Int to UInt conversion, recommended style for variables.
         */
@@ -77,7 +89,13 @@ package chisel3 {
     }
 
     implicit class fromStringToLiteral(val x: String) {
+      /** String to UInt parse, recommended style for constants.
+        */
       def U: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))       // scalastyle:ignore method.name
+
+      /** String to UInt parse, recommended style for variables.
+        */
+      def asUInt: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))
     }
 
     object fromStringToLiteral {
-- 
cgit v1.2.3


From c270598ddb8cbfa32f8c86cc5187c89d00e6ded0 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:22:31 -0800
Subject: Remove () from as_Int

---
 .../src/main/scala/chisel3/core/package.scala      | 31 ++++++++--------------
 1 file changed, 11 insertions(+), 20 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index cae64df6..3defb4f9 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -33,24 +33,16 @@ package chisel3 {
 
       /** Int to UInt conversion, recommended style for variables.
         */
-      def asUInt(): UInt = UInt.Lit(x, Width())
+      def asUInt: UInt = UInt.Lit(x, Width())
       /** Int to SInt conversion, recommended style for variables.
         */
-      def asSInt(): SInt = SInt.Lit(x, Width())
+      def asSInt: SInt = SInt.Lit(x, Width())
       /** Int to UInt conversion with specified width, recommended style for variables.
         */
       def asUInt(width: Width): UInt = UInt.Lit(x, width)
       /** Int to SInt conversion with specified width, recommended style for variables.
         */
       def asSInt(width: Width): SInt = SInt.Lit(x, width)
-
-      /** Int to UInt conversion with specified width, recommended style for variables.
-        */
-      //def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
-      /** Int to SInt conversion with specified width, recommended style for variables.
-        */
-      //def asSInt(width: Int): SInt = SInt(x, Width(width))
-
     }
 
     implicit class fromBigIntToLiteral(val x: BigInt) {
@@ -69,33 +61,32 @@ package chisel3 {
 
       /** Int to UInt conversion, recommended style for variables.
         */
-      def asUInt(): UInt = UInt.Lit(x, Width())
+      def asUInt: UInt = UInt.Lit(x, Width())
       /** Int to SInt conversion, recommended style for variables.
         */
-      def asSInt(): SInt = SInt.Lit(x, Width())
+      def asSInt: SInt = SInt.Lit(x, Width())
       /** Int to UInt conversion with specified width, recommended style for variables.
         */
       def asUInt(width: Width): UInt = UInt.Lit(x, width)
       /** Int to SInt conversion with specified width, recommended style for variables.
         */
       def asSInt(width: Width): SInt = SInt.Lit(x, width)
-
-      /** Int to UInt conversion with specified width, recommended style for variables.
-        */
-      // def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
-      /** Int to SInt conversion with specified width, recommended style for variables.
-        */
-      // def asSInt(width: Int): SInt = SInt(x, width)
     }
 
     implicit class fromStringToLiteral(val x: String) {
       /** String to UInt parse, recommended style for constants.
         */
-      def U: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))       // scalastyle:ignore method.name
+      def U: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))  // scalastyle:ignore method.name
+      /** String to UInt parse with specified width, recommended style for constants.
+        */
+      def U(width: Width): UInt = UInt.Lit(fromStringToLiteral.parse(x), width)  // scalastyle:ignore method.name
 
       /** String to UInt parse, recommended style for variables.
         */
       def asUInt: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))
+      /** String to UInt parse with specified width, recommended style for variables.
+        */
+      def asUInt(width: Width): UInt = UInt.Lit(fromStringToLiteral.parse(x), width)
     }
 
     object fromStringToLiteral {
-- 
cgit v1.2.3


From d89b54acc5a41dcc7498d97af314e58f6cd891c8 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:31:23 -0800
Subject: Refactor some code

---
 chiselFrontend/src/main/scala/chisel3/core/package.scala | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 3defb4f9..4a032523 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -76,21 +76,19 @@ package chisel3 {
     implicit class fromStringToLiteral(val x: String) {
       /** String to UInt parse, recommended style for constants.
         */
-      def U: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))  // scalastyle:ignore method.name
+      def U: UInt = UInt.Lit(parse(x), parsedWidth(x))  // scalastyle:ignore method.name
       /** String to UInt parse with specified width, recommended style for constants.
         */
-      def U(width: Width): UInt = UInt.Lit(fromStringToLiteral.parse(x), width)  // scalastyle:ignore method.name
+      def U(width: Width): UInt = UInt.Lit(parse(x), width)  // scalastyle:ignore method.name
 
       /** String to UInt parse, recommended style for variables.
         */
-      def asUInt: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))
+      def asUInt: UInt = UInt.Lit(parse(x), parsedWidth(x))
       /** String to UInt parse with specified width, recommended style for variables.
         */
-      def asUInt(width: Width): UInt = UInt.Lit(fromStringToLiteral.parse(x), width)
-    }
+      def asUInt(width: Width): UInt = UInt.Lit(parse(x), width)
 
-    object fromStringToLiteral {
-      def parse(n: String) = {
+      protected def parse(n: String) = {
         val (base, num) = n.splitAt(1)
         val radix = base match {
           case "x" | "h" => 16
@@ -102,7 +100,7 @@ package chisel3 {
         BigInt(num.filterNot(_ == '_'), radix)
       }
 
-      def parsedWidth(n: String) =
+      protected def parsedWidth(n: String) =
         if (n(0) == 'b') {
           Width(n.length-1)
         } else if (n(0) == 'h') {
-- 
cgit v1.2.3


From ebe7a0fb5774ec4bec919f9d3acd987d084d91b4 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:50:50 -0800
Subject: better style

---
 chiselFrontend/src/main/scala/chisel3/core/package.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 4a032523..7c11d446 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -128,4 +128,4 @@ package chisel3 {
       def W: Width = Width(x)  // scalastyle:ignore method.name
     }
   }
-}
\ No newline at end of file
+}
-- 
cgit v1.2.3


From 81e5d00d18a5ba9ae33c10219a270148002fc672 Mon Sep 17 00:00:00 2001
From: ducky
Date: Fri, 18 Nov 2016 13:36:03 -0800
Subject: Deboilerplate the implicit conversions, add support for long.U

---
 .../src/main/scala/chisel3/core/package.scala      | 71 +++++++---------------
 1 file changed, 23 insertions(+), 48 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 7c11d446..77f35c23 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -17,76 +17,51 @@ package chisel3 {
     * confusion (the 1 is a bit length and the 0 is a bit extraction position).
     * Prefer storing the result and then extracting from it.
     */
-    implicit class fromIntToLiteral(val x: Int) {
+    implicit class fromBigIntToLiteral(val bigint: BigInt) {
       /** Int to UInt conversion, recommended style for constants.
         */
-      def U: UInt = UInt.Lit(BigInt(x), Width())  // scalastyle:ignore method.name
+      def U: UInt = UInt.Lit(bigint, Width())  // scalastyle:ignore method.name
       /** Int to SInt conversion, recommended style for constants.
         */
-      def S: SInt = SInt.Lit(BigInt(x), Width())  // scalastyle:ignore method.name
+      def S: SInt = SInt.Lit(bigint, Width())  // scalastyle:ignore method.name
       /** Int to UInt conversion with specified width, recommended style for constants.
         */
-      def U(width: Width): UInt = UInt.Lit(BigInt(x), width)  // scalastyle:ignore method.name
+      def U(width: Width): UInt = UInt.Lit(bigint, width)  // scalastyle:ignore method.name
       /** Int to SInt conversion with specified width, recommended style for constants.
         */
-      def S(width: Width): SInt = SInt.Lit(BigInt(x), width)  // scalastyle:ignore method.name
+      def S(width: Width): SInt = SInt.Lit(bigint, width)  // scalastyle:ignore method.name
 
       /** Int to UInt conversion, recommended style for variables.
         */
-      def asUInt: UInt = UInt.Lit(x, Width())
+      def asUInt: UInt = UInt.Lit(bigint, Width())
       /** Int to SInt conversion, recommended style for variables.
         */
-      def asSInt: SInt = SInt.Lit(x, Width())
+      def asSInt: SInt = SInt.Lit(bigint, Width())
       /** Int to UInt conversion with specified width, recommended style for variables.
         */
-      def asUInt(width: Width): UInt = UInt.Lit(x, width)
+      def asUInt(width: Width): UInt = UInt.Lit(bigint, width)
       /** Int to SInt conversion with specified width, recommended style for variables.
         */
-      def asSInt(width: Width): SInt = SInt.Lit(x, width)
+      def asSInt(width: Width): SInt = SInt.Lit(bigint, width)
     }
 
-    implicit class fromBigIntToLiteral(val x: BigInt) {
-      /** Int to UInt conversion, recommended style for constants.
-        */
-      def U: UInt = UInt.Lit(x, Width())  // scalastyle:ignore method.name
-      /** Int to SInt conversion, recommended style for constants.
-        */
-      def S: SInt = SInt.Lit(x, Width())  // scalastyle:ignore method.name
-      /** Int to UInt conversion with specified width, recommended style for constants.
-        */
-      def U(width: Width): UInt = UInt.Lit(x, width)  // scalastyle:ignore method.name
-      /** Int to SInt conversion with specified width, recommended style for constants.
-        */
-      def S(width: Width): SInt = SInt.Lit(x, width)  // scalastyle:ignore method.name
-
-      /** Int to UInt conversion, recommended style for variables.
-        */
-      def asUInt: UInt = UInt.Lit(x, Width())
-      /** Int to SInt conversion, recommended style for variables.
-        */
-      def asSInt: SInt = SInt.Lit(x, Width())
-      /** Int to UInt conversion with specified width, recommended style for variables.
-        */
-      def asUInt(width: Width): UInt = UInt.Lit(x, width)
-      /** Int to SInt conversion with specified width, recommended style for variables.
-        */
-      def asSInt(width: Width): SInt = SInt.Lit(x, width)
-    }
+    implicit class fromIntToLiteral(val int: Int) extends fromBigIntToLiteral(int)
+    implicit class fromLongToLiteral(val long: Long) extends fromBigIntToLiteral(long)
 
-    implicit class fromStringToLiteral(val x: String) {
+    implicit class fromStringToLiteral(val str: String) {
       /** String to UInt parse, recommended style for constants.
         */
-      def U: UInt = UInt.Lit(parse(x), parsedWidth(x))  // scalastyle:ignore method.name
+      def U: UInt = UInt.Lit(parse(str), parsedWidth(str))  // scalastyle:ignore method.name
       /** String to UInt parse with specified width, recommended style for constants.
         */
-      def U(width: Width): UInt = UInt.Lit(parse(x), width)  // scalastyle:ignore method.name
+      def U(width: Width): UInt = UInt.Lit(parse(str), width)  // scalastyle:ignore method.name
 
       /** String to UInt parse, recommended style for variables.
         */
-      def asUInt: UInt = UInt.Lit(parse(x), parsedWidth(x))
+      def asUInt: UInt = UInt.Lit(parse(str), parsedWidth(str))
       /** String to UInt parse with specified width, recommended style for variables.
         */
-      def asUInt(width: Width): UInt = UInt.Lit(parse(x), width)
+      def asUInt(width: Width): UInt = UInt.Lit(parse(str), width)
 
       protected def parse(n: String) = {
         val (base, num) = n.splitAt(1)
@@ -110,22 +85,22 @@ package chisel3 {
         }
     }
 
-    implicit class fromBooleanToLiteral(val x: Boolean) {
+    implicit class fromBooleanToLiteral(val boolean: Boolean) {
       /** Boolean to Bool conversion, recommended style for constants.
         */
-      def B: Bool = Bool.Lit(x)  // scalastyle:ignore method.name
+      def B: Bool = Bool.Lit(boolean)  // scalastyle:ignore method.name
 
       /** Boolean to Bool conversion, recommended style for variables.
         */
-      def asBool: Bool = Bool.Lit(x)
+      def asBool: Bool = Bool.Lit(boolean)
     }
 
-    implicit class fromDoubleToLiteral(val x: Double) {
-      def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint)
+    implicit class fromDoubleToLiteral(val double: Double) {
+      def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(double, binaryPoint = binaryPoint)
     }
 
-    implicit class fromIntToWidth(val x: Int) {
-      def W: Width = Width(x)  // scalastyle:ignore method.name
+    implicit class fromIntToWidth(val int: Int) {
+      def W: Width = Width(int)  // scalastyle:ignore method.name
     }
   }
 }
-- 
cgit v1.2.3


From 11302f77c90512f81b882ad1cc623c53d45724f8 Mon Sep 17 00:00:00 2001
From: Donggyu
Date: Mon, 21 Nov 2016 14:52:05 -0800
Subject: Remove deduplication from Chisel (#347)

Remove modName from Module---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala      | 9 ---------
 chiselFrontend/src/main/scala/chisel3/internal/Builder.scala | 2 +-
 2 files changed, 1 insertion(+), 10 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 62b6d5ce..bd406529 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -124,18 +124,9 @@ extends HasId {
   /** Legalized name of this module. */
   final val name = Builder.globalNamespace.name(desiredName)
 
-  /** FIRRTL Module name */
-  private var _modName: Option[String] = None
-  private[chisel3] def setModName(name: String) = _modName = Some(name)
-  def modName = _modName match {
-    case Some(name) => name
-    case None => throwException("modName should be called after circuit elaboration")
-  }
-
   /** Keep component for signal names */
   private[chisel3] var _component: Option[Component] = None
 
-
   /** Signal name (for simulation). */
   override def instanceName =
     if (_parent == None) name else _component match {
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index 60ce6d5d..cf86b0e7 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -124,7 +124,7 @@ private[chisel3] trait HasId extends InstanceId {
     case None => throwException(s"$instanceName doesn't have a parent")
   }
   def parentModName = _parent match {
-    case Some(p) => p.modName
+    case Some(p) => p.name
     case None => throwException(s"$instanceName doesn't have a parent")
   }
 
-- 
cgit v1.2.3


From 3c31b9af6b1dc9abde701edb33d4be36c192bad2 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 21 Nov 2016 17:18:26 -0800
Subject: Fix toBits() deprecation message (to match what it effectively does).
 (#379)

Data.toUInt() doesn't exist.---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 2f18e726..57ed0c59 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -258,7 +258,7 @@ abstract class Data extends HasId {
     *
     * This performs the inverse operation of fromBits(Bits).
     */
-  @deprecated("Best alternative, .toUInt() or if Bits really needed, .toUInt().toBits()", "chisel3")
+  @deprecated("Best alternative, .asUInt()", "chisel3")
   def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo)
 
   /** Reinterpret cast to UInt.
-- 
cgit v1.2.3


From 8cb4e0cc38e2bf1ec596ae000caaf8e49c47dc31 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Tue, 22 Nov 2016 00:57:12 -0800
Subject: Disallow chained apply (#380)

---
 .../src/main/scala/chisel3/core/Aggregate.scala      |  2 +-
 .../src/main/scala/chisel3/core/Bits.scala           |  4 ++--
 .../src/main/scala/chisel3/core/package.scala        | 20 ++++++++++++--------
 3 files changed, 15 insertions(+), 11 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 8fdcb260..17354799 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -126,7 +126,7 @@ object Vec {
     if (n <= 1) 0.U
     else if (idx.width.known && idx.width.get <= w) idx
     else if (idx.width.known) idx(w-1,0)
-    else (idx | 0.U(w))(w-1,0)
+    else (idx | 0.U(w.W))(w-1,0)
   }
 }
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 354512e1..cab1a82e 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -478,7 +478,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
 
   final def unary_! () : Bool = macro SourceInfoTransform.noArg
 
-  def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === 0.U(1)
+  def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === 0.U(1.W)
 
   override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): UInt =
     binop(sourceInfo, UInt(this.width + that), ShiftLeftOp, that)
@@ -496,7 +496,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
   final def bitSet(off: UInt, dat: Bool): UInt = macro UIntTransform.bitset
 
   def do_bitSet(off: UInt, dat: Bool)(implicit sourceInfo: SourceInfo): UInt = {
-    val bit = 1.U(1) << off
+    val bit = 1.U(1.W) << off
     Mux(dat, this | bit, ~(~this | bit))
   }
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 77f35c23..1d5817ae 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -16,14 +16,18 @@ package chisel3 {
     * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
     * confusion (the 1 is a bit length and the 0 is a bit extraction position).
     * Prefer storing the result and then extracting from it.
+    *
+    * Implementation note: the empty parameter list (like `U()`) is necessary to prevent
+    * interpreting calls that have a non-Width parameter as a chained apply, otherwise things like
+    * `0.asUInt(16)` (instead of `16.W`) compile without error and produce undesired results.
     */
     implicit class fromBigIntToLiteral(val bigint: BigInt) {
       /** Int to UInt conversion, recommended style for constants.
         */
-      def U: UInt = UInt.Lit(bigint, Width())  // scalastyle:ignore method.name
+      def U(): UInt = UInt.Lit(bigint, Width())  // scalastyle:ignore method.name
       /** Int to SInt conversion, recommended style for constants.
         */
-      def S: SInt = SInt.Lit(bigint, Width())  // scalastyle:ignore method.name
+      def S(): SInt = SInt.Lit(bigint, Width())  // scalastyle:ignore method.name
       /** Int to UInt conversion with specified width, recommended style for constants.
         */
       def U(width: Width): UInt = UInt.Lit(bigint, width)  // scalastyle:ignore method.name
@@ -33,10 +37,10 @@ package chisel3 {
 
       /** Int to UInt conversion, recommended style for variables.
         */
-      def asUInt: UInt = UInt.Lit(bigint, Width())
+      def asUInt(): UInt = UInt.Lit(bigint, Width())
       /** Int to SInt conversion, recommended style for variables.
         */
-      def asSInt: SInt = SInt.Lit(bigint, Width())
+      def asSInt(): SInt = SInt.Lit(bigint, Width())
       /** Int to UInt conversion with specified width, recommended style for variables.
         */
       def asUInt(width: Width): UInt = UInt.Lit(bigint, width)
@@ -51,14 +55,14 @@ package chisel3 {
     implicit class fromStringToLiteral(val str: String) {
       /** String to UInt parse, recommended style for constants.
         */
-      def U: UInt = UInt.Lit(parse(str), parsedWidth(str))  // scalastyle:ignore method.name
+      def U(): UInt = UInt.Lit(parse(str), parsedWidth(str))  // scalastyle:ignore method.name
       /** String to UInt parse with specified width, recommended style for constants.
         */
       def U(width: Width): UInt = UInt.Lit(parse(str), width)  // scalastyle:ignore method.name
 
       /** String to UInt parse, recommended style for variables.
         */
-      def asUInt: UInt = UInt.Lit(parse(str), parsedWidth(str))
+      def asUInt(): UInt = UInt.Lit(parse(str), parsedWidth(str))
       /** String to UInt parse with specified width, recommended style for variables.
         */
       def asUInt(width: Width): UInt = UInt.Lit(parse(str), width)
@@ -88,11 +92,11 @@ package chisel3 {
     implicit class fromBooleanToLiteral(val boolean: Boolean) {
       /** Boolean to Bool conversion, recommended style for constants.
         */
-      def B: Bool = Bool.Lit(boolean)  // scalastyle:ignore method.name
+      def B(): Bool = Bool.Lit(boolean)  // scalastyle:ignore method.name
 
       /** Boolean to Bool conversion, recommended style for variables.
         */
-      def asBool: Bool = Bool.Lit(boolean)
+      def asBool(): Bool = Bool.Lit(boolean)
     }
 
     implicit class fromDoubleToLiteral(val double: Double) {
-- 
cgit v1.2.3


From edb19a0559686a471141c74438f677c1e217a298 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Wed, 23 Nov 2016 16:01:50 -0800
Subject: Simplify Enum API (#385)

Get rid of some cruft exposed in #373

This also allows Bits.fromtInt(...) to be removed. Yay!

All old APIs (with some new restrictions, rocket still works fine) are preserved without deprecation in Chisel._, aside from the non-compile-time-checkable Map[] enum constructor which probably should have been deprecated during chisel2. The Map[] enums have been removed from chisel3._ without deprecation.

The new restriction is that nodeType (legacy API) may only be of UInt type with unspecified width. Note that Bits() creates a UInt, and if you can't control the enum values, it makes little sense to specify a bitwidth.---
 chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 17 -----------------
 1 file changed, 17 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index cab1a82e..035ac213 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -54,8 +54,6 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
   // Arguments for: self-checking code (can't do arithmetic on bits)
   // Arguments against: generates down to a FIRRTL UInt anyways
 
-  private[chisel3] def fromInt(x: BigInt, w: Int): this.type
-
   private[chisel3] def flatten: IndexedSeq[Bits] = IndexedSeq(this)
 
   def cloneType: this.type = cloneTypeWidth(width)
@@ -402,9 +400,6 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
     new UInt(w).asInstanceOf[this.type]
   private[chisel3] def toType = s"UInt$width"
 
-  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
-    value.asUInt(width.W).asInstanceOf[this.type]
-
   // TODO: refactor to share documentation with Num or add independent scaladoc
   final def unary_- (): UInt = macro SourceInfoTransform.noArg
   final def unary_-% (): UInt = macro SourceInfoTransform.noArg
@@ -562,9 +557,6 @@ sealed class SInt private[core] (width: Width, lit: Option[SLit] = None)
     new SInt(w).asInstanceOf[this.type]
   private[chisel3] def toType = s"SInt$width"
 
-  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
-    value.asSInt(width.W).asInstanceOf[this.type]
-
   final def unary_- (): SInt = macro SourceInfoTransform.noArg
   final def unary_-% (): SInt = macro SourceInfoTransform.noArg
 
@@ -696,11 +688,6 @@ sealed class Bool(lit: Option[ULit] = None) extends UInt(1.W, lit) {
     new Bool().asInstanceOf[this.type]
   }
 
-  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = {
-    require((value == 0 || value == 1) && width == 1)
-    (value == 1).asBool.asInstanceOf[this.type]
-  }
-
   // REVIEW TODO: Why does this need to exist and have different conventions
   // than Bits?
   final def & (that: Bool): Bool = macro SourceInfoTransform.thatArg
@@ -823,10 +810,6 @@ sealed class FixedPoint private (width: Width, val binaryPoint: BinaryPoint, lit
     case _ => this badConnect that
   }
 
-  private[chisel3] def fromInt(value: BigInt, width: Int): this.type = {
-    throwException(s"Don't use $this.fromInt($value, $width): Use literal constructors instead")
-  }
-
   final def unary_- (): FixedPoint = macro SourceInfoTransform.noArg
   final def unary_-% (): FixedPoint = macro SourceInfoTransform.noArg
 
-- 
cgit v1.2.3


From 7680363982b02f53e9f76f5d5e242e44f17da6f7 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Tue, 29 Nov 2016 16:37:13 -0800
Subject: Add feature warnings to build, fix feature warnings, fix some
 documentation (#387)

---
 chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 17354799..9bbf9d0e 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -225,7 +225,7 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
   private[chisel3] lazy val flatten: IndexedSeq[Bits] =
     (0 until length).flatMap(i => this.apply(i).flatten)
 
-  for ((elt, i) <- self zipWithIndex)
+  for ((elt, i) <- self.zipWithIndex)
     elt.setRef(this, i)
 
   /** Default "pretty-print" implementation
-- 
cgit v1.2.3


From 6725dbd501e3d3a0d6a626f69473115069ac3b34 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 1 Dec 2016 17:34:39 -0800
Subject: Fix spelling of "specified". (#392)

---
 chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 262b939f..699cc13c 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -64,7 +64,7 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
   protected def minWidth: Int
   if (forcedWidth) {
     require(widthArg.get >= minWidth,
-      s"The literal value ${num} was elaborated with a specificed width of ${widthArg.get} bits, but at least ${minWidth} bits are required.")
+      s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.")
   }
 }
 
-- 
cgit v1.2.3


From a1e8ae80888b6b4d7bac057c6486b3442334cdc6 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Mon, 5 Dec 2016 11:28:04 -0800
Subject: Fix literal width (#389)

Fixes #388---
 .../src/main/scala/chisel3/core/package.scala          | 18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 1d5817ae..87dca1f3 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -55,14 +55,17 @@ package chisel3 {
     implicit class fromStringToLiteral(val str: String) {
       /** String to UInt parse, recommended style for constants.
         */
-      def U(): UInt = UInt.Lit(parse(str), parsedWidth(str))  // scalastyle:ignore method.name
+      def U(): UInt = str.asUInt() // scalastyle:ignore method.name
       /** String to UInt parse with specified width, recommended style for constants.
         */
-      def U(width: Width): UInt = UInt.Lit(parse(str), width)  // scalastyle:ignore method.name
+      def U(width: Width): UInt = str.asUInt(width) // scalastyle:ignore method.name
 
       /** String to UInt parse, recommended style for variables.
         */
-      def asUInt(): UInt = UInt.Lit(parse(str), parsedWidth(str))
+      def asUInt(): UInt = {
+        val bigInt = parse(str)
+        UInt.Lit(bigInt, Width(bigInt.bitLength max 1))
+      }
       /** String to UInt parse with specified width, recommended style for variables.
         */
       def asUInt(width: Width): UInt = UInt.Lit(parse(str), width)
@@ -78,15 +81,6 @@ package chisel3 {
         }
         BigInt(num.filterNot(_ == '_'), radix)
       }
-
-      protected def parsedWidth(n: String) =
-        if (n(0) == 'b') {
-          Width(n.length-1)
-        } else if (n(0) == 'h') {
-          Width((n.length-1) * 4)
-        } else {
-          Width()
-        }
     }
 
     implicit class fromBooleanToLiteral(val boolean: Boolean) {
-- 
cgit v1.2.3


From ad53161bbb9f67e16b88ca7a508a537f88d77e05 Mon Sep 17 00:00:00 2001
From: Chick Markley
Date: Wed, 7 Dec 2016 10:31:23 -0800
Subject: Support for creating chisel annotations that are consumed by firrtl
 (#393)

* Support for creating chisel annotations that are consumed by firrtl
Update annotation serialization in Driver
Add DiamondAnnotation Spec that illustrates how to do simple annotations
frontEnd must have dependency on firrtl
Add annotation method to Module
Circuit has extra optional parameter that is Seq of Annotations
In Builder add annotation buffer to DynamicContext to store annotations created in modules
Added explicit types on naming api methods to avoid type confusion
Because some names are not available until elaboration create intermediate ChiselAnnotation that
gets turned into a firrtl Annotation after elaboration
In execute pass firrtl text and annotation to firrtl are now passed in through optionManager, though
intermediate file .fir and .anno files are still created for inspection and/or later use

* Somehow missed ChiselAnnotation

* fixes for Jack's review of PR
---
 .../main/scala/chisel3/core/ChiselAnnotation.scala | 30 ++++++++++++++++++++++
 .../src/main/scala/chisel3/core/Module.scala       |  6 ++++-
 .../src/main/scala/chisel3/internal/Builder.scala  | 12 +++++----
 .../main/scala/chisel3/internal/firrtl/IR.scala    |  4 ++-
 4 files changed, 45 insertions(+), 7 deletions(-)
 create mode 100644 chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala b/chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala
new file mode 100644
index 00000000..73573bb1
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala
@@ -0,0 +1,30 @@
+// See LICENSE for license details.
+
+package chisel3.core
+
+import chisel3.internal.InstanceId
+import firrtl.Transform
+import firrtl.annotations.{Annotation, CircuitName, ComponentName, ModuleName}
+
+/**
+  * This is a stand-in for the firrtl.Annotations.Annotation because at the time this annotation
+  * is created the component cannot be resolved, into a targetString.  Resolution can only
+  * happen after the circuit is elaborated
+  * @param component       A chisel thingy to be annotated, could be module, wire, reg, etc.
+  * @param transformClass  A fully-qualified class name of the transformation pass
+  * @param value           A string value to be used by the transformation pass
+  */
+case class ChiselAnnotation(component: InstanceId, transformClass: Class[_ <: Transform], value: String) {
+  def toFirrtl: Annotation = {
+    val circuitName = CircuitName(component.pathName.split("""\.""").head)
+    component match {
+      case m: Module =>
+        Annotation(
+          ModuleName(m.name, circuitName), transformClass, value)
+      case _ =>
+        Annotation(
+          ComponentName(
+            component.instanceName, ModuleName(component.parentModName, circuitName)), transformClass, value)
+    }
+  }
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index bd406529..76a3b240 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -14,7 +14,7 @@ object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
     * (necessary to help Chisel track internal state).
     *
-    * @param m the Module being created
+    * @param bc the Module being created
     *
     * @return the input module `m` with Chisel metadata properly set
     */
@@ -85,6 +85,10 @@ extends HasId {
     iodef
   }
 
+  def annotate(annotation: ChiselAnnotation): Unit = {
+    Builder.annotations += annotation
+  }
+
   private[core] var ioDefined: Boolean = false
 
   /**
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index cf86b0e7..7a77763b 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -108,22 +108,22 @@ private[chisel3] trait HasId extends InstanceId {
   private[chisel3] def getRef: Arg = _ref.get
 
   // Implementation of public methods.
-  def instanceName = _parent match {
+  def instanceName: String = _parent match {
     case Some(p) => p._component match {
       case Some(c) => getRef fullName c
       case None => throwException("signalName/pathName should be called after circuit elaboration")
     }
     case None => throwException("this cannot happen")
   }
-  def pathName = _parent match {
+  def pathName: String = _parent match {
     case None => instanceName
     case Some(p) => s"${p.pathName}.$instanceName"
   }
-  def parentPathName = _parent match {
+  def parentPathName: String = _parent match {
     case Some(p) => p.pathName
     case None => throwException(s"$instanceName doesn't have a parent")
   }
-  def parentModName = _parent match {
+  def parentModName: String = _parent match {
     case Some(p) => p.name
     case None => throwException(s"$instanceName doesn't have a parent")
   }
@@ -145,6 +145,7 @@ private[chisel3] class DynamicContext() {
   val idGen = new IdGen
   val globalNamespace = new Namespace(None, Set())
   val components = ArrayBuffer[Component]()
+  val annotations = ArrayBuffer[ChiselAnnotation]()
   var currentModule: Option[Module] = None
   // Set by object Module.apply before calling class Module constructor
   // Used to distinguish between no Module() wrapping, multiple wrappings, and rewrapping
@@ -161,6 +162,7 @@ private[chisel3] object Builder {
   def idGen: IdGen = dynamicContext.idGen
   def globalNamespace: Namespace = dynamicContext.globalNamespace
   def components: ArrayBuffer[Component] = dynamicContext.components
+  def annotations: ArrayBuffer[ChiselAnnotation] = dynamicContext.annotations
 
   def currentModule: Option[Module] = dynamicContext.currentModule
   def currentModule_=(target: Option[Module]): Unit = {
@@ -206,7 +208,7 @@ private[chisel3] object Builder {
       errors.checkpoint()
       errors.info("Done elaborating.")
 
-      Circuit(components.last.name, components)
+      Circuit(components.last.name, components, annotations.map(_.toFirrtl))
     }
   }
 }
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 699cc13c..50400034 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -7,6 +7,8 @@ import core._
 import chisel3.internal._
 import chisel3.internal.sourceinfo.{SourceInfo, NoSourceInfo}
 
+import _root_.firrtl.annotations.Annotation
+
 case class PrimOp(val name: String) {
   override def toString: String = name
 }
@@ -273,4 +275,4 @@ abstract class Component extends Arg {
 case class DefModule(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
 case class DefBlackBox(id: Module, name: String, ports: Seq[Port], params: Map[String, Param]) extends Component
 
-case class Circuit(name: String, components: Seq[Component])
+case class Circuit(name: String, components: Seq[Component], annotations: Seq[Annotation] = Seq.empty)
-- 
cgit v1.2.3