From e98f9656591925464c42db70641d3cfa501f108a Mon Sep 17 00:00:00 2001 From: chick Date: Mon, 6 Jun 2016 15:03:36 -0700 Subject: Changed deprecation warning for Data#toBits to recommend asUInt instead because the sole remaining use of toBits in chiselTests was to compare to Vectors declared differently but with same underlying bits. Making at toBits was problematic because it did not support === method. Changed Vec and Bundle to both support toUInt() Note: If toBits is actually needed now, one can use toInt().toBits() --- chiselFrontend/src/main/scala/Chisel/Aggregate.scala | 11 +++++++++++ chiselFrontend/src/main/scala/Chisel/Data.scala | 4 +++- 2 files changed, 14 insertions(+), 1 deletion(-) (limited to 'chiselFrontend') diff --git a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala index 1eef5d69..8af4e9e9 100644 --- a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala +++ b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala @@ -167,6 +167,11 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) private[Chisel] lazy val flatten: IndexedSeq[Bits] = (0 until length).flatMap(i => this.apply(i).flatten) + /** Reinterpret cast to UInt. */ + def asUInt(): UInt = macro SourceInfoTransform.noArg + + def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() + for ((elt, i) <- self zipWithIndex) elt.setRef(this, i) } @@ -341,6 +346,12 @@ class Bundle extends Aggregate(NO_DIR) { private[Chisel] lazy val flatten = namedElts.flatMap(_._2.flatten) private[Chisel] def addElt(name: String, elt: Data): Unit = namedElts += name -> elt + + /** Reinterpret cast to UInt. */ + def asUInt(): UInt = macro SourceInfoTransform.noArg + + def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() + private[Chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) } diff --git a/chiselFrontend/src/main/scala/Chisel/Data.scala b/chiselFrontend/src/main/scala/Chisel/Data.scala index d16843f7..adb4ff7b 100644 --- a/chiselFrontend/src/main/scala/Chisel/Data.scala +++ b/chiselFrontend/src/main/scala/Chisel/Data.scala @@ -117,8 +117,10 @@ abstract class Data(dirArg: Direction) extends HasId { * * This performs the inverse operation of fromBits(Bits). */ - @deprecated("Use asBits, which makes the reinterpret cast more explicit and actually returns Bits", "chisel3") + @deprecated("Best alternative, .toUInt() or if Bits really needed, .toUInt().toBits()", "chisel3") def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo) + +// def asBits(): Bits } object Wire { -- cgit v1.2.3 From 43124af2f3eab9a3491dd2c83c1922b1b7e07c2a Mon Sep 17 00:00:00 2001 From: chick Date: Mon, 6 Jun 2016 15:32:33 -0700 Subject: moved macro def for toUInt() int to Data and made do_asUInt (the macro target) there as an abstract method. This left clock without a do_asUInt, that has been implemented as an exception at this time --- chiselFrontend/src/main/scala/Chisel/Aggregate.scala | 6 ------ chiselFrontend/src/main/scala/Chisel/Bits.scala | 12 ------------ chiselFrontend/src/main/scala/Chisel/Data.scala | 15 ++++++++++++++- 3 files changed, 14 insertions(+), 19 deletions(-) (limited to 'chiselFrontend') diff --git a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala index 8af4e9e9..f573592d 100644 --- a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala +++ b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala @@ -167,9 +167,6 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) private[Chisel] lazy val flatten: IndexedSeq[Bits] = (0 until length).flatMap(i => this.apply(i).flatten) - /** Reinterpret cast to UInt. */ - def asUInt(): UInt = macro SourceInfoTransform.noArg - def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() for ((elt, i) <- self zipWithIndex) @@ -347,9 +344,6 @@ class Bundle extends Aggregate(NO_DIR) { private[Chisel] def addElt(name: String, elt: Data): Unit = namedElts += name -> elt - /** Reinterpret cast to UInt. */ - def asUInt(): UInt = macro SourceInfoTransform.noArg - def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() private[Chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name diff --git a/chiselFrontend/src/main/scala/Chisel/Bits.scala b/chiselFrontend/src/main/scala/Chisel/Bits.scala index bc8cc8e2..ee6b1dee 100644 --- a/chiselFrontend/src/main/scala/Chisel/Bits.scala +++ b/chiselFrontend/src/main/scala/Chisel/Bits.scala @@ -210,15 +210,6 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: def do_asSInt(implicit sourceInfo: SourceInfo): SInt - /** Reinterpret cast to an UInt. - * - * @note value not guaranteed to be preserved: for example, a SInt of width - * 3 and value -1 (0b111) would become an UInt with value 7 - */ - final def asUInt(): UInt = macro SourceInfoTransform.noArg - - def do_asUInt(implicit sourceInfo: SourceInfo): UInt - /** Reinterpret cast to Bits. */ final def asBits(): Bits = macro SourceInfoTransform.noArg @@ -250,9 +241,6 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: pushOp(DefPrim(sourceInfo, UInt(w), ConcatOp, this.ref, that.ref)) } - @deprecated("Use asBits, which makes the reinterpret cast more explicit and actually returns Bits", "chisel3") - override def toBits: UInt = do_asUInt(DeprecatedSourceInfo) - override def do_fromBits(that: Bits)(implicit sourceInfo: SourceInfo): this.type = { val res = Wire(this, null).asInstanceOf[this.type] res := that diff --git a/chiselFrontend/src/main/scala/Chisel/Data.scala b/chiselFrontend/src/main/scala/Chisel/Data.scala index adb4ff7b..b953df71 100644 --- a/chiselFrontend/src/main/scala/Chisel/Data.scala +++ b/chiselFrontend/src/main/scala/Chisel/Data.scala @@ -120,7 +120,15 @@ abstract class Data(dirArg: Direction) extends HasId { @deprecated("Best alternative, .toUInt() or if Bits really needed, .toUInt().toBits()", "chisel3") def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo) -// def asBits(): Bits + /** Reinterpret cast to a UInt. + * + * @note value not guaranteed to be preserved: for example, a SInt of width + * 3 and value -1 (0b111) would become an UInt with value 7 + */ + final def asUInt(): UInt = macro SourceInfoTransform.noArg + + def do_asUInt(implicit sourceInfo: SourceInfo): UInt + } object Wire { @@ -160,4 +168,9 @@ sealed class Clock(dirArg: Direction) extends Element(dirArg, Width(1)) { case _: Clock => this connect that case _ => this badConnect that } + + def do_asUInt(implicit sourceInfo: SourceInfo): UInt = { + throwException("clock cannot be interpreted as UInt") + } + } -- cgit v1.2.3 From b7c6e0d1a2098b545938a5a8dfce2b1d9294532f Mon Sep 17 00:00:00 2001 From: chick Date: Mon, 6 Jun 2016 15:57:28 -0700 Subject: moved do_asUInt implementation into aggregate, it has been to identical separate implementations in Vec and Bundle --- chiselFrontend/src/main/scala/Chisel/Aggregate.scala | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'chiselFrontend') diff --git a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala index f573592d..c0f8a354 100644 --- a/chiselFrontend/src/main/scala/Chisel/Aggregate.scala +++ b/chiselFrontend/src/main/scala/Chisel/Aggregate.scala @@ -17,6 +17,8 @@ import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, VecTransform, Sour sealed abstract class Aggregate(dirArg: Direction) extends Data(dirArg) { private[Chisel] def cloneTypeWidth(width: Width): this.type = cloneType def width: Width = flatten.map(_.width).reduce(_ + _) + + def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten) } object Vec { @@ -167,8 +169,6 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) private[Chisel] lazy val flatten: IndexedSeq[Bits] = (0 until length).flatMap(i => this.apply(i).flatten) - def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() - for ((elt, i) <- self zipWithIndex) elt.setRef(this, i) } @@ -344,8 +344,6 @@ class Bundle extends Aggregate(NO_DIR) { private[Chisel] def addElt(name: String, elt: Data): Unit = namedElts += name -> elt - def do_asUInt(implicit sourceInfo: SourceInfo): UInt = SeqUtils.do_asUInt(this.flatten).asUInt() - private[Chisel] override def _onModuleClose: Unit = // scalastyle:ignore method.name for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) } -- cgit v1.2.3