From a931abe0cf57481b47093b5950d3bffd9575f803 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 28 Jun 2018 17:34:05 -0700
Subject: Change [public] Data.elementLitArg => [protected]
 Aggregate.litArgOfBits

---
 chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 4 ++++
 chiselFrontend/src/main/scala/chisel3/core/Bits.scala      | 6 ++----
 chiselFrontend/src/main/scala/chisel3/core/Data.scala      | 4 ----
 3 files changed, 6 insertions(+), 8 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 54932bcc..9bb24e43 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -64,6 +64,10 @@ sealed abstract class Aggregate extends Data {
 
   def litToBigIntOption: Option[BigInt] = ???  // TODO implement me
 
+  // Returns the LitArg of a Bits object.
+  // Internal API for Bundle literals, to copy the LitArg of argument literals into the top map.
+  protected def litArgOfBits(elt: Bits): LitArg = elt.litArgOption.get
+
   /** Returns a Seq of the immediate contents of this Aggregate, in order.
     */
   def getElements: Seq[Data]
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index d39cc088..a8ebab1b 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -81,15 +81,13 @@ sealed abstract class Bits(width: Width)
     case topBindingOpt => topBindingOpt
   }
 
-  protected def litArgOption: Option[LitArg] = topBindingOpt match {
+  private[core] def litArgOption: Option[LitArg] = topBindingOpt match {
     case Some(ElementLitBinding(litArg)) => Some(litArg)
     case _ => None
   }
 
   override def litToBigIntOption: Option[BigInt] = litArgOption.map(_.num)
-  private[chisel3] def litIsForcedWidth: Option[Boolean] = litArgOption.map(_.forcedWidth)
-
-  override def elementLitArg: Option[LitArg] = litArgOption
+  private[core] def litIsForcedWidth: Option[Boolean] = litArgOption.map(_.forcedWidth)
 
   // provide bits-specific literal handling functionality here
   override private[chisel3] def ref: Arg = topBindingOpt match {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index d3d94b21..466f976e 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -398,10 +398,6 @@ abstract class Data extends HasId with NamedComponent {
   @deprecated("isLit is deprecated, use litToBigIntOption or litTo*Option", "chisel3.2")
   def isLit(): Boolean = litArg.isDefined
 
-  // If this is an element literal, returns the LitArg bound to it.
-  // INTERNAL API, but this isn't protected to allow bundle literal constructors.
-  def elementLitArg: Option[LitArg] = None
-
   /**
    * If this is a literal that is representable as bits, returns the value as a BigInt.
    * If not a literal, or not representable as bits (for example, is or contains Analog), returns None.
-- 
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