From a06c411ce2ce6ddf8c20b38f90f4074af7b33b3f Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Fri, 6 Mar 2020 11:05:55 -0800
Subject: Provide API to set concrete type of implicit reset (#1361)

Introduces mutually-exclusive traits RequireAsyncReset and
RequireSyncReset to set the type of the implicit reset in
MultiIOModules. The Scala-type remains Reset, but the Chisel
elaboration-time checks apply.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 chiselFrontend/src/main/scala/chisel3/RawModule.scala | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/RawModule.scala b/chiselFrontend/src/main/scala/chisel3/RawModule.scala
index ae3b6fe7..407ed931 100644
--- a/chiselFrontend/src/main/scala/chisel3/RawModule.scala
+++ b/chiselFrontend/src/main/scala/chisel3/RawModule.scala
@@ -134,6 +134,14 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
   }
 }
 
+trait RequireAsyncReset extends MultiIOModule {
+  override private[chisel3] def mkReset: AsyncReset = AsyncReset()
+}
+
+trait RequireSyncReset extends MultiIOModule {
+  override private[chisel3] def mkReset: Bool = Bool()
+}
+
 /** Abstract base class for Modules, which behave much like Verilog modules.
   * These may contain both logic and state which are written in the Module
   * body (constructor).
@@ -145,10 +153,12 @@ abstract class MultiIOModule(implicit moduleCompileOptions: CompileOptions)
     extends RawModule {
   // Implicit clock and reset pins
   val clock: Clock = IO(Input(Clock()))
-  val reset: Reset = {
+  val reset: Reset = IO(Input(mkReset))
+
+  private[chisel3] def mkReset: Reset = {
     // Top module and compatibility mode use Bool for reset
     val inferReset = _parent.isDefined && moduleCompileOptions.inferModuleReset
-    IO(Input(if (inferReset) Reset() else Bool()))
+    if (inferReset) Reset() else Bool()
   }
 
   // Setup ClockAndReset
-- 
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