From 64a8f52c48905e9bf28e709cde2de89215a35c80 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 31 Jul 2018 14:11:33 -0700
Subject: Ensure names work for bundles and literals. (#853)

Fixes #852---
 chiselFrontend/src/main/scala/chisel3/core/Bits.scala   | 15 +++++++--------
 .../src/main/scala/chisel3/internal/Builder.scala       |  6 +++++-
 .../src/main/scala/chisel3/internal/firrtl/IR.scala     | 17 +++++++++++++++--
 3 files changed, 27 insertions(+), 11 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 35f6c978..10b6ec8e 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -604,8 +604,7 @@ trait UIntFactory {
     val lit = ULit(value, width)
     val result = new UInt(lit.width)
     // Bind result to being an Literal
-    result.bind(ElementLitBinding(lit))
-    result
+    lit.bindLitArg(result)
   }
 
   /** Create a UInt with the specified range */
@@ -757,8 +756,7 @@ trait SIntFactory {
   protected[chisel3] def Lit(value: BigInt, width: Width): SInt = {
     val lit = SLit(value, width)
     val result = new SInt(lit.width)
-    result.bind(ElementLitBinding(lit))
-    result
+    lit.bindLitArg(result)
   }
 }
 
@@ -828,8 +826,9 @@ trait BoolFactory {
    */
   protected[chisel3] def Lit(x: Boolean): Bool = {
     val result = new Bool()
-    result.bind(ElementLitBinding(ULit(if (x) 1 else 0, Width(1))))
-    result
+    val lit = ULit(if (x) 1 else 0, Width(1))
+    // Ensure we have something capable of generating a name.
+    lit.bindLitArg(result)
   }
 }
 
@@ -1086,8 +1085,8 @@ object FixedPoint {
   def apply(value: BigInt, width: Width, binaryPoint: BinaryPoint): FixedPoint = {
     val lit = FPLit(value, width, binaryPoint)
     val newLiteral = new FixedPoint(lit.width, lit.binaryPoint)
-    newLiteral.bind(ElementLitBinding(lit))
-    newLiteral
+    // Ensure we have something capable of generating a name.
+    lit.bindLitArg(newLiteral)
   }
 
   /**
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index 360994b1..ce4e1e88 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -112,11 +112,15 @@ private[chisel3] trait HasId extends InstanceId {
   private[chisel3] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
   private[chisel3] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
   private[chisel3] def getRef: Arg = _ref.get
+  private[chisel3] def getOptionRef: Option[Arg] = _ref
 
   // Implementation of public methods.
   def instanceName: String = _parent match {
     case Some(p) => p._component match {
-      case Some(c) => getRef fullName c
+      case Some(c) => _ref match {
+        case Some(arg) => arg fullName c
+        case None => suggested_name.getOrElse("??")
+      }
       case None => throwException("signalName/pathName should be called after circuit elaboration")
     }
     case None => throwException("this cannot happen")
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 6b555a82..b6630f7f 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -53,13 +53,26 @@ abstract class Arg {
 }
 
 case class Node(id: HasId) extends Arg {
-  override def fullName(ctx: Component): String = id.getRef.fullName(ctx)
-  def name: String = id.getRef.name
+  override def fullName(ctx: Component): String = id.getOptionRef match {
+    case Some(arg) => arg.fullName(ctx)
+    case None => id.suggestedName.getOrElse("??")
+  }
+  def name: String = id.getOptionRef match {
+    case Some(arg) => arg.name
+    case None => id.suggestedName.getOrElse("??")
+  }
 }
 
 abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
   private[chisel3] def forcedWidth = widthArg.known
   private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
+  override def fullName(ctx: Component): String = name
+  // Ensure the node representing this LitArg has a ref to it and a literal binding.
+  def bindLitArg[T <: Bits](bits: T): T = {
+    bits.bind(ElementLitBinding(this))
+    bits.setRef(this)
+    bits
+  }
 
   protected def minWidth: Int
   if (forcedWidth) {
-- 
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