From 5509cdd4c8332c53151e10ba5bdbe0684af1c05b Mon Sep 17 00:00:00 2001
From: Martin Schoeberl
Date: Fri, 25 Jan 2019 23:24:01 -0800
Subject: WireDefault instead of WireInit, keep WireInit around (#986)

---
 .../src/main/scala/chisel3/core/Aggregate.scala    |  2 +-
 .../src/main/scala/chisel3/core/Data.scala         | 26 ++++++++++++----------
 2 files changed, 15 insertions(+), 13 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index e85b7158..fa23ddaa 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -90,7 +90,7 @@ sealed abstract class Aggregate extends Data {
   private[core] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
       compileOptions: CompileOptions): Unit = {
     var i = 0
-    val bits = WireInit(UInt(this.width), that)  // handles width padding
+    val bits = WireDefault(UInt(this.width), that)  // handles width padding
     for (x <- flatten) {
       x.connectFromBits(bits(i + x.getWidth - 1, i))
       i += x.getWidth
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index bffd84df..06fb27cc 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -564,9 +564,10 @@ trait WireFactory {
   */
 object Wire extends WireFactory
 
+
 /** Utility for constructing hardware wires with a default connection
   *
-  * The two forms of `WireInit` differ in how the type and width of the resulting [[Wire]] are
+  * The two forms of `WireDefault` differ in how the type and width of the resulting [[Wire]] are
   * specified.
   *
   * ==Single Argument==
@@ -577,16 +578,16 @@ object Wire extends WireFactory
   *
   * 1. Literal [[Bits]] initializer: width will be set to match
   * {{{
-  * val w1 = WireInit(1.U) // width will be inferred to be 1
-  * val w2 = WireInit(1.U(8.W)) // width is set to 8
+  * val w1 = WireDefault(1.U) // width will be inferred to be 1
+  * val w2 = WireDefault(1.U(8.W)) // width is set to 8
   * }}}
   *
   * 2. Non-Literal [[Element]] initializer - width will be inferred
   * {{{
   * val x = Wire(UInt())
   * val y = Wire(UInt(8.W))
-  * val w1 = WireInit(x) // width will be inferred
-  * val w2 = WireInit(y) // width will be inferred
+  * val w1 = WireDefault(x) // width will be inferred
+  * val w2 = WireDefault(y) // width will be inferred
   * }}}
   *
   * 3. [[Aggregate]] initializer - width will be set to match the aggregate
@@ -597,7 +598,7 @@ object Wire extends WireFactory
   *   val known   = UInt(8.W)
   * }
   * val w1 = Wire(new MyBundle)
-  * val w2 = WireInit(w1)
+  * val w2 = WireDefault(w1)
   * // Width of w2.unknown is inferred
   * // Width of w2.known is set to 8
   * }}}
@@ -606,24 +607,24 @@ object Wire extends WireFactory
   * The double argument form allows the type of the [[Wire]] and the default connection to be
   * specified independently.
   *
-  * The width inference semantics for `WireInit` with two arguments match those of [[Wire]]. The
-  * first argument to `WireInit` is the type template which defines the width of the `Wire` in
+  * The width inference semantics for `WireDefault` with two arguments match those of [[Wire]]. The
+  * first argument to `WireDefault` is the type template which defines the width of the `Wire` in
   * exactly the same way as the only argument to [[Wire]].
   *
-  * More explicitly, you can reason about `WireInit` with multiple arguments as if it were defined
+  * More explicitly, you can reason about `WireDefault` with multiple arguments as if it were defined
   * as:
   * {{{
-  * def WireInit[T <: Data](t: T, init: T): T = {
+  * def WireDefault[T <: Data](t: T, init: T): T = {
   *   val x = Wire(t)
   *   x := init
   *   x
   * }
   * }}}
   *
-  * @note The `Init` in `WireInit` refers to a `default` connection. This is in contrast to
+  * @note The `Default` in `WireDefault` refers to a `default` connection. This is in contrast to
   * [[RegInit]] where the `Init` refers to a value on reset.
   */
-object WireInit {
+object WireDefault {
 
   private def applyImpl[T <: Data](t: T, init: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
     implicit val noSourceInfo = UnlocatableSourceInfo
@@ -696,3 +697,4 @@ object DontCare extends Element {
   // DontCare's only match themselves.
   private[core] def typeEquivalent(that: chisel3.core.Data): Boolean = that == DontCare
 }
+
-- 
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