From aea7e1e754a3ebdb5b7e84c3ae1d35b16e547823 Mon Sep 17 00:00:00 2001
From: Donggyu Kim
Date: Sun, 23 Oct 2016 19:20:33 -0700
Subject: create SeqMems' read ports inside when statement

this helps firrtl to infer read enable signals
---
 chiselFrontend/src/main/scala/chisel3/core/Mem.scala | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index 9cd5a4d8..a43b19fe 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -147,7 +147,11 @@ sealed class SeqMem[T <: Data](t: T, n: Int) extends MemBase[T](t, n) {
   def read(addr: UInt, enable: Bool): T = {
     implicit val sourceInfo = UnlocatableSourceInfo
     val a = Wire(UInt())
-    when (enable) { a := addr }
-    read(a)
+    var port: Option[T] = None
+    when (enable) {
+      a := addr
+      port = Some(read(a))
+    }
+    port.get
   }
 }
-- 
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