From 32acdcf63ab74e7d47d7600f2211a72dd19280c3 Mon Sep 17 00:00:00 2001
From: Edward Wang
Date: Wed, 10 Apr 2019 00:16:48 -0700
Subject: Fix wrong directionality for Vec(Flipped())

Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.

Close #1063
---
 .../src/main/scala/chisel3/core/RawModule.scala       | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

(limited to 'chiselFrontend')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala b/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala
index 00e78295..b1cae1b7 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala
@@ -85,7 +85,24 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
       id._onModuleClose
     }
 
-    val firrtlPorts = getModulePorts map {port => Port(port, port.specifiedDirection)}
+    val firrtlPorts = getModulePorts map { port: Data =>
+      // Special case Vec to make FIRRTL emit the direction of its
+      // element.
+      // Just taking the Vec's specifiedDirection is a bug in cases like
+      // Vec(Flipped()), since the Vec's specifiedDirection is
+      // Unspecified.
+      val direction = port match {
+        case v: Vec[_] => v.specifiedDirection match {
+          case SpecifiedDirection.Input => SpecifiedDirection.Input
+          case SpecifiedDirection.Output => SpecifiedDirection.Output
+          case SpecifiedDirection.Flip => SpecifiedDirection.flip(v.sample_element.specifiedDirection)
+          case SpecifiedDirection.Unspecified => v.sample_element.specifiedDirection
+        }
+        case _ => port.specifiedDirection
+      }
+
+      Port(port, direction)
+    }
     _firrtlPorts = Some(firrtlPorts)
 
     // Generate IO invalidation commands to initialize outputs as unused,
-- 
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