From e1e7c7ea3359df1351ba979287b62458e411e846 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Mon, 8 Aug 2016 16:54:05 -0700 Subject: Provide public SignalID trait to be used to conjure up a signal identifier. --- .../src/main/scala/chisel3/core/Module.scala | 3 +++ .../src/main/scala/chisel3/internal/Builder.scala | 21 ++++++++++++++++++++- 2 files changed, 23 insertions(+), 1 deletion(-) (limited to 'chiselFrontend') diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 5af744c4..4f25515b 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -63,6 +63,9 @@ extends HasId { /** Legalized name of this module. */ final val name = Builder.globalNamespace.name(desiredName) + /** Signal name (for simulation). */ + override def signalName(component: Component) = name + /** IO for this Module. At the Scala level (pre-FIRRTL transformations), * connections in and out of a Module may only go through `io` elements. */ diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index cecbd91e..dd4b3264 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -55,11 +55,30 @@ private[chisel3] class IdGen { } } -private[chisel3] trait HasId { +/** Public API to Nodes. + * currently, the node's name, the full path name, and a reference to its parent. + */ +trait SignalID { + def signalName(component: Component): String + def signalPathName(component: Component, separator: String = "_"): String + def signalParent: Module +} + +private[chisel3] trait HasId extends SignalID { private[chisel3] def _onModuleClose {} // scalastyle:ignore method.name private[chisel3] val _parent = Builder.dynamicContext.currentModule _parent.foreach(_.addId(this)) + // Implementation of public methods. + override def signalParent = _parent.get + override def signalName(component: Component) = _ref.get.fullName(component) + override def signalPathName(component: Component, separator: String = "_"): String = { + _parent match { + case Some(p) => p.signalPathName(component, separator) + separator + signalName(component) + case None => signalName(component) + } + } + private[chisel3] val _id = Builder.idGen.next override def hashCode: Int = _id.toInt override def equals(that: Any): Boolean = that match { -- cgit v1.2.3 From 0744b3e5f9c0648878b97d3375cd7d88e2d0ee08 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Wed, 10 Aug 2016 17:07:31 -0700 Subject: Add component to signature. --- chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 3 +-- chiselFrontend/src/main/scala/chisel3/internal/Builder.scala | 9 ++++++--- 2 files changed, 7 insertions(+), 5 deletions(-) (limited to 'chiselFrontend') diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 15643ac8..de64cb3d 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -374,5 +374,4 @@ class Bundle extends Aggregate(NO_DIR) { private[core] object Bundle { val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits", - "widthOption") -} + "widthOption", "signalName", "signalPathName", "signalParent", "signalComponent") diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index dd4b3264..21f32483 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -55,13 +55,15 @@ private[chisel3] class IdGen { } } -/** Public API to Nodes. - * currently, the node's name, the full path name, and a reference to its parent. +/** Public API to access Node/Signal names. + * currently, the node's name, the full path name, and references to its parent Module and component. + * These are only valid once the design has been elaborated, and should not be used during its construction. */ trait SignalID { def signalName(component: Component): String - def signalPathName(component: Component, separator: String = "_"): String + def signalPathName(component: Component, separator: String = "."): String def signalParent: Module + def signalComponent: Option[Component] } private[chisel3] trait HasId extends SignalID { @@ -78,6 +80,7 @@ private[chisel3] trait HasId extends SignalID { case None => signalName(component) } } + override def signalComponent: Option[Component] = None private[chisel3] val _id = Builder.idGen.next override def hashCode: Int = _id.toInt -- cgit v1.2.3 From 2d01fdf6f26f480cb7ed19c1365f181ea717ddc2 Mon Sep 17 00:00:00 2001 From: Donggyu Kim Date: Mon, 15 Aug 2016 18:03:12 -0700 Subject: provides signal name methods for firrtl annotation and chisel testers * signalName: returns the chirrtl name of the signal * pathName: returns the full path name of the signal from the top module * parentPathName: returns the full path of the signal's parent module instance from the top module * parentModName: returns the signal's parent **module(not instance)** name. --- .../src/main/scala/chisel3/core/Aggregate.scala | 3 +- .../src/main/scala/chisel3/core/Module.scala | 22 ++++++++++- .../src/main/scala/chisel3/internal/Builder.scala | 44 +++++++++++++--------- 3 files changed, 49 insertions(+), 20 deletions(-) (limited to 'chiselFrontend') diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index de64cb3d..82c6097f 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -374,4 +374,5 @@ class Bundle extends Aggregate(NO_DIR) { private[core] object Bundle { val keywords = List("flip", "asInput", "asOutput", "cloneType", "toBits", - "widthOption", "signalName", "signalPathName", "signalParent", "signalComponent") + "widthOption", "signalName", "signalPathName", "signalParent", "signalComponent") +} diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 4f25515b..eb48a14d 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -31,7 +31,9 @@ object Module { m._commands.prepend(DefInvalid(childSourceInfo, m.io.ref)) // init module outputs dynamicContext.currentModule = parent val ports = m.computePorts - Builder.components += Component(m, m.name, ports, m._commands) + val component = Component(m, m.name, ports, m._commands) + m._component = Some(component) + Builder.components += component pushCommand(DefInstance(sourceInfo, m, ports)) m.setupInParent(childSourceInfo) } @@ -63,8 +65,24 @@ extends HasId { /** Legalized name of this module. */ final val name = Builder.globalNamespace.name(desiredName) + /** FIRRTL Module name */ + private var _modName: Option[String] = None + private[chisel3] def setModName(name: String) = _modName = Some(name) + def modName = _modName match { + case Some(name) => name + case None => throwException("modName should be called after circuit elaboration") + } + + /** Keep component for signal names */ + private[chisel3] var _component: Option[Component] = None + + /** Signal name (for simulation). */ - override def signalName(component: Component) = name + override def signalName = + if (_parent == None) name else _component match { + case None => getRef.name + case Some(c) => getRef fullName c + } /** IO for this Module. At the Scala level (pre-FIRRTL transformations), * connections in and out of a Module may only go through `io` elements. diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index 21f32483..bf78c410 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -59,29 +59,18 @@ private[chisel3] class IdGen { * currently, the node's name, the full path name, and references to its parent Module and component. * These are only valid once the design has been elaborated, and should not be used during its construction. */ -trait SignalID { - def signalName(component: Component): String - def signalPathName(component: Component, separator: String = "."): String - def signalParent: Module - def signalComponent: Option[Component] +trait SignalId { + def signalName: String + def pathName: String + def parentPathName: String + def parentModName: String } -private[chisel3] trait HasId extends SignalID { +private[chisel3] trait HasId extends SignalId { private[chisel3] def _onModuleClose {} // scalastyle:ignore method.name private[chisel3] val _parent = Builder.dynamicContext.currentModule _parent.foreach(_.addId(this)) - // Implementation of public methods. - override def signalParent = _parent.get - override def signalName(component: Component) = _ref.get.fullName(component) - override def signalPathName(component: Component, separator: String = "_"): String = { - _parent match { - case Some(p) => p.signalPathName(component, separator) + separator + signalName(component) - case None => signalName(component) - } - } - override def signalComponent: Option[Component] = None - private[chisel3] val _id = Builder.idGen.next override def hashCode: Int = _id.toInt override def equals(that: Any): Boolean = that match { @@ -117,6 +106,27 @@ private[chisel3] trait HasId extends SignalID { private[chisel3] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index))) private[chisel3] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref)) private[chisel3] def getRef: Arg = _ref.get + + // Implementation of public methods. + def signalName = _parent match { + case Some(p) => p._component match { + case Some(c) => getRef fullName c + case None => throwException("signalName/pathName should be called after circuit elaboration") + } + case None => throwException("this cannot happen") + } + def pathName = _parent match { + case None => signalName + case Some(p) => s"${p.pathName}.$signalName" + } + def parentPathName = _parent match { + case Some(p) => p.pathName + case None => throwException(s"$signalName doesn't have a parent") + } + def parentModName = _parent match { + case Some(p) => p.modName + case None => throwException(s"$signalName doesn't have a parent") + } } private[chisel3] class DynamicContext { -- cgit v1.2.3 From f5e9a6c6e55ba19a7c1f2353d0207189062db1c9 Mon Sep 17 00:00:00 2001 From: chick Date: Wed, 24 Aug 2016 17:09:41 -0700 Subject: Per Chisel meeting. signalName -> instanceName SignalId -> InstanceId Based on Stephen's comments on PR --- chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 +- .../src/main/scala/chisel3/internal/Builder.scala | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'chiselFrontend') diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index eb48a14d..2426ae78 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -78,7 +78,7 @@ extends HasId { /** Signal name (for simulation). */ - override def signalName = + override def instanceName = if (_parent == None) name else _component match { case None => getRef.name case Some(c) => getRef fullName c diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index bf78c410..2dec78bb 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -59,14 +59,14 @@ private[chisel3] class IdGen { * currently, the node's name, the full path name, and references to its parent Module and component. * These are only valid once the design has been elaborated, and should not be used during its construction. */ -trait SignalId { - def signalName: String +trait InstanceId { + def instanceName: String def pathName: String def parentPathName: String def parentModName: String } -private[chisel3] trait HasId extends SignalId { +private[chisel3] trait HasId extends InstanceId { private[chisel3] def _onModuleClose {} // scalastyle:ignore method.name private[chisel3] val _parent = Builder.dynamicContext.currentModule _parent.foreach(_.addId(this)) @@ -108,7 +108,7 @@ private[chisel3] trait HasId extends SignalId { private[chisel3] def getRef: Arg = _ref.get // Implementation of public methods. - def signalName = _parent match { + def instanceName = _parent match { case Some(p) => p._component match { case Some(c) => getRef fullName c case None => throwException("signalName/pathName should be called after circuit elaboration") @@ -116,16 +116,16 @@ private[chisel3] trait HasId extends SignalId { case None => throwException("this cannot happen") } def pathName = _parent match { - case None => signalName - case Some(p) => s"${p.pathName}.$signalName" + case None => instanceName + case Some(p) => s"${p.pathName}.$instanceName" } def parentPathName = _parent match { case Some(p) => p.pathName - case None => throwException(s"$signalName doesn't have a parent") + case None => throwException(s"$instanceName doesn't have a parent") } def parentModName = _parent match { case Some(p) => p.modName - case None => throwException(s"$signalName doesn't have a parent") + case None => throwException(s"$instanceName doesn't have a parent") } } -- cgit v1.2.3