From 9e99adbe920f3127e02a8dac05c972e3ea518c12 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 7 Aug 2019 18:00:29 -0400 Subject: Require target is hardware for Vec.apply(a: UInt) Adds a check that a Vec being indexed by a UInt is, in fact, a hardware type. This includes a test for this. Signed-off-by: Schuyler Eldridge --- chiselFrontend/src/main/scala/chisel3/Aggregate.scala | 1 + 1 file changed, 1 insertion(+) (limited to 'chiselFrontend/src') diff --git a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala index 9149447a..dfba1caf 100644 --- a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala @@ -216,6 +216,7 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) /** @group SourceInfoTransformMacro */ def do_apply(p: UInt)(implicit compileOptions: CompileOptions): T = { + requireIsHardware(this, "vec") requireIsHardware(p, "vec index") val port = gen -- cgit v1.2.3