From 1183e98cfd0626f879177f693682c917f28e3d62 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Thu, 21 Mar 2019 15:57:32 -0700
Subject: Change == to reference equality (eq) in Data print (#1044)

---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 45afed94..64c84c05 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -314,7 +314,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // sc
     case Some(MemoryPortBinding(enclosure)) => s"(MemPort in ${enclosure.desiredName})"
     case Some(PortBinding(enclosure)) if !enclosure.isClosed => s"(IO in unelaborated ${enclosure.desiredName})"
     case Some(PortBinding(enclosure)) if enclosure.isClosed =>
-      DataMirror.fullModulePorts(enclosure).find(_._2 == this) match {
+      DataMirror.fullModulePorts(enclosure).find(_._2 eq this) match {
         case Some((name, _)) => s"(IO $name in ${enclosure.desiredName})"
         case None => s"(IO (unknown) in ${enclosure.desiredName})"
       }
-- 
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