From 22f9c43cfd617407f687eb35154ea18f16626f5b Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Fri, 6 Mar 2020 11:48:19 -0800
Subject: Make implicit clock and reset final vals (#1360)

Overriding will always result in a NullPointerException---
 chiselFrontend/src/main/scala/chisel3/RawModule.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend/src/main')

diff --git a/chiselFrontend/src/main/scala/chisel3/RawModule.scala b/chiselFrontend/src/main/scala/chisel3/RawModule.scala
index 407ed931..218022cc 100644
--- a/chiselFrontend/src/main/scala/chisel3/RawModule.scala
+++ b/chiselFrontend/src/main/scala/chisel3/RawModule.scala
@@ -152,8 +152,8 @@ trait RequireSyncReset extends MultiIOModule {
 abstract class MultiIOModule(implicit moduleCompileOptions: CompileOptions)
     extends RawModule {
   // Implicit clock and reset pins
-  val clock: Clock = IO(Input(Clock()))
-  val reset: Reset = IO(Input(mkReset))
+  final val clock: Clock = IO(Input(Clock()))
+  final val reset: Reset = IO(Input(mkReset))
 
   private[chisel3] def mkReset: Reset = {
     // Top module and compatibility mode use Bool for reset
-- 
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