From 095fd80cc1250f5ec242fde6ccc9271665f784b2 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 4 Oct 2016 11:46:13 -0700
Subject: Add CompileOptions implicits to all Module constructors - fix #310.
 (#311)

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'chiselFrontend/src/main')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 6fb6d036..55522b4a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -54,9 +54,9 @@ abstract class Module(
 extends HasId {
   // _clock and _reset can be clock and reset in these 2ary constructors
   // once chisel2 compatibility issues are resolved
-  def this(_clock: Clock) = this(Option(_clock), None)
-  def this(_reset: Bool)  = this(None, Option(_reset))
-  def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset))
+  def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), None)(moduleCompileOptions)
+  def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions)  = this(None, Option(_reset))(moduleCompileOptions)
+  def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions)
 
   // This function binds the iodef as a port in the hardware graph
   private[chisel3] def Port[T<:Data](iodef: T): iodef.type = {
-- 
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